Patents by Inventor Benyang WU

Benyang WU has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RISC-V-based 3D interconnected multi-core processor architecture and working method thereof
    Patent number: 11714649
    Abstract: An RISC-V-based 3D interconnected multi-core processor architecture and a working method thereof. The RISC-V-based 3D interconnected multi-core processor architecture includes a main control layer, a micro core array layer and an accelerator layer, wherein the main control layer includes a plurality of main cores which are RISC-V instruction set CPU cores, the micro core array layer includes a plurality of micro unit groups including a micro core, a data storage unit, an instruction storage unit and a linking controller, wherein the micro core is an RISC-V instruction set CPU core that executes partial functions of the main core; the accelerator layer is configured to optimize a running speed of space utilization for accelerators meeting specific requirements, wherein some main cores in the main control layer perform data interaction with the accelerator layer, the other main cores interact with the micro core array layer.
    Type: Grant
    Filed: December 1, 2021
    Date of Patent: August 1, 2023
    Assignee: SHANDONG LINGNENG ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Gang Wang, Jinzheng Mou, Yang An, Moujun Xie, Benyang Wu, Zesheng Zhang, Wenyong Hou, Yongwei Wang, Zixuan Qiu, Xintan Li
  • RISC-V-BASED 3D INTERCONNECTED MULTI-CORE PROCESSOR ARCHITECTURE AND WORKING METHOD THEREOF
    Publication number: 20230168892
    Abstract: An RISC-V-based 3D interconnected multi-core processor architecture and a working method thereof. The RISC-V-based 3D interconnected multi-core processor architecture includes a main control layer, a micro core array layer and an accelerator layer, wherein the main control layer includes a plurality of main cores which are RISC-V instruction set CPU cores, the micro core array layer includes a plurality of micro unit groups including a micro core, a data storage unit, an instruction storage unit and a linking controller, wherein the micro core is an RISC-V instruction set CPU core that executes partial functions of the main core; the accelerator layer is configured to optimize a running speed of space utilization for accelerators meeting specific requirements, wherein some main cores in the main control layer perform data interaction with the accelerator layer, the other main cores interact with the micro core array layer.
    Type: Application
    Filed: December 1, 2021
    Publication date: June 1, 2023
    Applicant: SHANDONG LINGNENG ELECTRONIC TECHNOLOGY CO., LTD.
    Inventors: Gang WANG, Jinzheng MOU, Yang AN, Moujun XIE, Benyang WU, Zesheng ZHANG, Wenyong HOU, Yongwei WANG, Zixuan QIU, Xintan LI