Patents by Inventor Benyong Zhang
Benyong Zhang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240007091Abstract: A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value.Type: ApplicationFiled: September 13, 2023Publication date: January 4, 2024Inventors: Madusudanan Srinivasan Gopalan, Christopher Schell, Benyong Zhang
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Patent number: 11799460Abstract: A clock generator circuit including an integer divider, having a first input receiving a reference clock and configured to generate an intermediate clock at a frequency divided down from a frequency of the reference clock by an integer value, a digital delay stage configured to generate a delayed intermediate clock delayed from the intermediate clock by a number of fractional cycles of the reference clock selected responsive to a fractional cycle value, and an analog delay stage configured to generate an output clock delayed from the delayed intermediate clock by a delay value selected responsive to a fine adjustment value. The clock generator circuit further includes math engine circuitry configured to compute a phase adjustment code responsive to the phase adjustment word, the phase adjustment code comprising the integer value, the fractional cycle value, and the fine adjustment value.Type: GrantFiled: June 29, 2022Date of Patent: October 24, 2023Assignee: Texas Instruments IncorporatedInventors: Madusudanan Srinivasan Gopalan, Christopher Schell, Benyong Zhang
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Patent number: 9680484Abstract: Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation.Type: GrantFiled: December 2, 2015Date of Patent: June 13, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Benyong Zhang, Anjin Du, Junqiang Shi
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Publication number: 20160164532Abstract: Disclosed is a circuit, such as a clock conditioner, that provides an improved ability to exit from holdover operations, most notably during conditions where the clock signal inputs to a PLL of the clock conditioner are significantly out of phase. The circuit utilizes the PLL to generate output clocks based on a reference clock and a feedback clock. During holdover mode, the PLL is unlocked. When the reference clock becomes available and holdover mode can be exited, a holdover controller issues a reset signal that triggers a synchronization of the phases of the inputs to the PLL. The reset signal causes the feedback divider component that generates the feedback clock input to reset its phase and adjust its divide ratio for at least the first divide cycle after restart so that its next rising edge will be phase-aligned with the reference clock. Once the two inputs of the PLL phase detector are phase-aligned, the PLL is re-enabled and the PLL smoothly resumes normal operation.Type: ApplicationFiled: December 2, 2015Publication date: June 9, 2016Applicant: Texas Instruments IncorporatedInventors: Benyong Zhang, Anjin Du, Junqiang Shi
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Patent number: 9140751Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously. An output short circuit current fault is indicated when the voltage drop across any of the resistors exceeds a threshold value corresponding to a maximum output short circuit current value.Type: GrantFiled: March 27, 2013Date of Patent: September 22, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Chee Peng Ong, Wen Hui Woon, Benyong Zhang, Eric Lindgren
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Publication number: 20140292361Abstract: An electronic package having multiple pins may be tested in parallel for output short circuit current by simulating a direct short to ground by simultaneously connecting multiple output pins directly to ground in order to active a current limiter associated with each of the output pins. The pins are then connected to a resistive connection to ground via a set of resistors; the direct ground is then removed, such that the current limiter associated with each of the output pins remains activated. A voltage drop across each of the set of resistors is measured simultaneously.Type: ApplicationFiled: March 27, 2013Publication date: October 2, 2014Applicant: Texas Instruments IncorporatedInventors: Chee Peng Ong, Wen Hui Woon, Benyong Zhang, Eric Lindgren
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Patent number: 8502575Abstract: A fractional spur compensation technique is implemented in a fractional-N PLL using multiple phase comparison frequencies Fpd, one of which is selected for any channel frequency Fch in a target frequency band to obtain a selected offset frequency Fos between the channel frequency Fch and its primary fractional spur throughout the target frequency band. Other features of an exemplary implementation of the fractional spur compensation technique include (a) maintaining the phase comparison frequency at less than a predetermined maximum value, (b) using a programmable reference frequency multiplier with selectable multiplication factors and/or a programmable reference frequency divider with selectable divide ratios to generate multiple phase comparison frequencies derived from a predetermined reference frequency Fref, and (c) using a programmable charge pump to select different charge pump currents for respective phase comparison frequencies to reduce loop gain variation.Type: GrantFiled: September 23, 2011Date of Patent: August 6, 2013Assignee: Texas Instruments IncorporatedInventor: Benyong Zhang
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Publication number: 20120074995Abstract: SEARCHES A fractional spur compensation technique is implemented in a fractional-N PLL using multiple phase comparison frequencies Fpd, one of which is selected for any channel frequency Fch in a target frequency band to obtain a selected offset frequency Fos between the channel frequency Fch and its primary fractional spur throughout the target frequency band. Other features of an exemplary implementation of the fractional spur compensation technique include (a) maintaining the phase comparison frequency at less than a predetermined maximum value, (b) using a programmable reference frequency multiplier with selectable multiplication factors and/or a programmable reference frequency divider with selectable divide ratios to generate multiple phase comparison frequencies derived from a predetermined reference frequency Fref, and (c) using a programmable charge pump to select different charge pump currents for respective phase comparison frequencies to reduce loop gain variation.Type: ApplicationFiled: September 23, 2011Publication date: March 29, 2012Applicant: National Semiconductor CorporationInventor: Benyong ZHANG
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Patent number: 8102196Abstract: A clock signal generator and conditioner in which dual integrated phase-locked loop (PLL) circuits use an off-chip frequency-pullable crystal resonator or voltage-controlled oscillator (VCO) module and an on-chip VCO with intra-PLL frequency doubling to provide a clock signal with reduced in-band phase noise and RMS jitter. As desired, synchronization between the input and output clocks can also be provided.Type: GrantFiled: April 14, 2010Date of Patent: January 24, 2012Assignee: National Semiconductor CorporationInventor: Benyong Zhang
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Patent number: 7038509Abstract: A method for providing a phase-locked loop with reduced spurious tones is provided that includes comparing a reference clock signal to an internal clock signal to generate a first signal. The first signal is sampled based on a sampling clock signal to generate a second signal. The sampling clock signal is reduced with respect to the reference clock signal. The internal clock signal is generated based on the second signal.Type: GrantFiled: October 27, 2003Date of Patent: May 2, 2006Assignee: National Semiconductor CorporationInventor: Benyong Zhang