Abstract: As an electroless plating technique capable of surely promoting the plating reaction without Pd substitution reaction and fastening the plating deposition, there are proposed an electroless plating method of subjecting a primary plated film (or metal film) formed on a substrate to a secondary plating (or electroless plating), characterized in that the secondary plating is carried out after a surface potential of the primary plated film is adjusted so as to be more base than such a most base surface potential that a surface current density of the primary plated film is zero in an electroless plating solution for the secondary plating; and a pretreating solution for electroless plating comprising an alkali solution, reducing agent and completing agent; and an electroless plating bath suitable for use in this method.

Abstract: As an electroless plating technique capable of surely promoting the plating reaction without Pd substitution reaction and fastening the plating deposition, there are proposed an electroless plating method of subjecting a primary plated film (or metal film) formed on a substrate to a secondary plating (or electroless plating), characterized in that the secondary plating is carried out after a surface potential of the primary plated film is adjusted so as to be more base than such a most base surface potential that a surface current density of the primary plated film is zero in an electroless plating solution for the secondary plating; and a pretreating solution for electroless plating comprising an alkali solution, reducing agent and complexing agent; and an electroless plating bath suitable for use in this method.

Abstract: A semiconductor package (11) includes a high density multi-layered printed wiring board (12), a plurality of LSI chips (14,15) and a substrate supporter (13). A substrate (16) is made of a material having higher heat conductivity than that of resins. A build-up layer (17) having interlayer insulations (I1-I4) and conductive layers (C1-C5) is formed on a first side (S1) of the substrate (16). A die area (19) for mounting the LSI chips (14,15) is provided on the build-up layer (17). A plurality of I/O pads (21) are provided around the die area. The I/O pads (21) are connected to bonding pads (28) on the supporter (13) via bonding wires. The supporter (13) includes a printed wiring board (23) consisting essentially of a resin material. The wiring board (12) is fitted in a window (24) formed in the printed wiring board (23) while a second side (S2) of the substrate, which is opposite to the first side, is exposed from the window.