Abstract: A Network-on-Chip (NoC) system employing an Advanced extensible Interface (AXI) protocol is provided. The NoC includes an NoC router which classifies data transmitted from a plurality of AXI Intellectual Properties (IPs) according to a destination AXI IP, and a network interface (NI) which processes data from the NoC router and provides the processed data to the destination IP. One of the NoC router and the NI includes a plurality of buffers which store data provided from each of the AXI IPs and classified according to each of the AXI IPs, and an interleaving manager which selects buffers, from which data is retrieved, among the plurality of buffers according to an interleaving acceptance capability which is a number of interleaving data that can be accepted by the destination AXI IP.

Abstract: A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

Abstract: System-on-a-chip using a CDMA bus and data transmission method therefor. The system-on-a-chip has plural IP-cores dividing into at least one group according to a predetermined reference; and at least one arbiter connected to the IP-cores belonging to the at least one group, receiving a unique ID of a reception-side IP-core receiving data from a transmission-side IP-core sending the data, and sending the transmission-side IP-core a code word assigned to the reception-side IP-core corresponding to the received unique ID, thereby reducing the length of the code word assigned to the IP-cores.