Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.

Abstract: A semiconductor device including a tapered spacer and method for manufacturing the same are disclosed. The semiconductor device includes a conductive-line contact plug and a conductive pattern spaced apart from each other in a first direction; a conductive line disposed over the conductive-line contact plug and extending in a second direction perpendicular to the first direction; and a spacer structure configured to contact sidewalls of the conductive line and the conductive-line contact plug, and configured such that a width of an upper portion of the spacer structure is narrower than a width of a lower portion of the spacer structure.

Abstract: A semiconductor device includes: a trench formed in a substrate; a buried conductive layer that gap-fills a portion of the trench; and a capping structure that gap-fills a remaining portion of the trench over the buried conductive layer and includes a carbon-containing material. In the semiconductor device, junction strain may be minimized by reducing the tensile stress of a capping layer.

Abstract: A semiconductor device may include a plurality of active regions delimited on a substrate. A plurality of bit line structures crossing over the plurality of the active regions may be provided. A plurality of storage node contacts may be disposed between the plurality of the bit line structures. A plug isolation pattern may be disposed between the plurality of the storage node contacts. The plug isolation pattern may include an isolation insulating layer between the plurality of the storage node contacts; and a tapered dielectric layer between the isolation insulating layer and the plurality of the storage node contacts.

Abstract: Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive lines and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises: a conductive line formed over a substrate; and a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material.

Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.

Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.

Abstract: Embodiments of the present invention provide a semiconductor device capable of reducing parasitic capacitance between neighboring conductive lines and a method for fabricating the same. According to an embodiment of the present invention, a semiconductor device comprises: a conductive line formed over a substrate; and a multi-layered spacer covering both sidewalls of the conductive line, wherein the multi-layered spacer is stacked in the order of a diffusion barrier material, boron nitride layer, and an antioxidant material.

Abstract: A semiconductor device includes: a semiconductor device, comprising: a bit line structure including a bit line contact plug, a bit line, and a bit line hard mask that are sequentially stacked over a substrate; a storage node contact plug that is spaced apart from the bit line structure; a conformal spacer that is positioned between the bit line and the storage node contact plug and includes a low-k material; and a seed liner that is positioned between the conformal spacer and the bit line and thinner than the conformal spacer.

Abstract: The present invention provides a smart contact lens including a sensor capable of non-invasively sensing an eye disease in real time and a drug reservoir, and smart glasses for controlling the smart contact lens.

Abstract: The present invention provides a smart contact lens including a sensor capable of non-invasively sensing an eye disease in real time and a drug reservoir, and smart glasses for controlling the smart contact lens.

Abstract: Provided are a phase-change memory device using insulating nanoparticles, a flexible phase-change memory device and a method for manufacturing the same. The phase-change memory device includes an electrode, and a phase-change layer in which a phase change occurs depending on heat generated from the electrode, wherein insulating nanoparticles formed from a self-assembled block copolymer are provided between the electrode and the phase-change layer undergoing crystallization and amorphization.

Abstract: Provided are a phase-change memory device using insulating nanoparticles, a flexible phase-change memory device and a method for manufacturing the same. The phase-change memory device includes an electrode, and a phase-change layer in which a phase change occurs depending on heat generated from the electrode, wherein insulating nanoparticles formed from a self-assembled block copolymer are provided between the electrode and the phase-change layer undergoing crystallization and amorphization.