Abstract: The present disclosure relates to semiconductor devices. An example semiconductor device includes a substrate including first and second regions, a first bridge pattern extending in a first direction on the first region, a first gate structure extending in a second direction intersecting the first direction, first epitaxial patterns connected to the first bridge pattern on side surfaces of the first gate structure, first inner spacers interposed between the substrate and the first bridge pattern and between the first gate structure and the first epitaxial patterns, a second bridge pattern extending in the first direction on the second region, a second gate structure extending in the second direction, second epitaxial patterns connected to the second bridge pattern on side surfaces of the second gate structure, and second inner spacers interposed between the substrate and the second bridge pattern and between the second gate structure and the second epitaxial patterns.

Abstract: A semiconductor device is provided. The semiconductor includes at least one of a well area in a substrate and having a first conductivity-type; impurity-implanted areas in the well, and having a second conductivity-type different from the first conductivity-type and arranged in a first direction, a first fin structure on the impurity-implanted area and having the second conductivity-type, wherein the first fin structure includes first semiconductor patterns and first sacrificial patterns alternately stacked; a first contact on the first fin structure; a first epitaxial pattern on the well area and having the first conductivity-type; and a second contact on the first epitaxial pattern.

Abstract: A semiconductor device is provided. The semiconductor includes a substrate having a first conductivity type; a well region having a second conductivity type in the substrate; an impurity implantation region having the first conductivity type in the well region; an element separation pattern in the substrate; a first fin pattern defined by the element separation pattern in the impurity implantation region; a second fin pattern defined by the element separation pattern in the well region; and a third fin pattern defined by the element separation pattern in the substrate, wherein the first fin pattern is a single fin, and an entirety of a lower boundary of the impurity implantation region is in contact with the well region.

Abstract: The present invention relates to a prefabricated chair and, more particularly, to a prefabricated chair separated into two frames so that the volume thereof can be remarkably reduced, thereby facilitating storage and transportation and enabling easy assembly without a separate tool.

Abstract: A semiconductor device includes a substrate that includes a first region and a second region, a first active pattern on the first region, a first gate structure that intersects the first active pattern, a first epitaxial pattern connected to the first active pattern and includes n-type impurities, a first source/drain contact that penetrates an upper surface of the first epitaxial pattern and is connected to the first epitaxial pattern, a second active pattern on the second region, a second gate structure that intersects the second active pattern, a second epitaxial pattern connected to the second active pattern and includes p-type impurities, and a second source/drain contact that penetrates an upper surface of the second epitaxial pattern and is connected to the second epitaxial pattern. A lower surface of the first source/drain contact is lower than a lower surface of the second source/drain contact.

Abstract: A semiconductor device including a substrate, a first and second active pattern extending in a first horizontal direction on the substrate, the second active pattern apart from the first active pattern in the first horizontal direction, first nanosheets apart from each other in a vertical direction on the first active pattern, second nanosheets apart from each other in the vertical direction on the first and second active patterns, a gate electrode extending in a second horizontal direction different from the first horizontal direction on the first active pattern and surrounding the first nanosheets, a source/drain region between the first and second nanosheets, an active cut penetrating the second nanosheets in the vertical direction, extending to the substrate, and separating the first and second active patterns, and a sacrificial layer between the source/drain region and the active cut, in contact with the active cut, and including silicon germanium may be provided.

Abstract: The present invention relates to a prefabricated chair and, more particularly, to a prefabricated chair separated into two frames so that the volume thereof can be remarkably reduced, thereby facilitating storage and transportation and enabling easy assembly without a separate tool.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOI substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: A semiconductor device includes first to fourth active patterns extending in a horizontal first direction. The second active pattern is spaced apart from the first active pattern in the first direction. The third active pattern is spaced apart from the first active pattern in a horizontal second direction. The fourth active pattern is spaced apart from the third active pattern in the first direction. A field insulating layer surrounds a sidewall of each of the first to fourth active patterns. First to fourth pluralities of nanosheets are respectively disposed the first to fourth active patterns. A first gate electrode extends in the second direction, intersects each of the first and third active patterns, and surrounds the first and third pluralities of nanosheets. A second gate electrode extends in the second direction, intersects each of the second and fourth active patterns, and surrounds the second and fourth pluralities of nanosheets.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

Abstract: A semiconductor device that reduces the occurrence of a leakage current by forming a doped layer in each of an NMOS region and a PMOS region on an SOT substrate, and completely separating the doped layer of the NMOS region from the doped layer of the PMOS region using the element isolation layer is provided. The semiconductor device includes a first region and a second region adjacent to the first region, a substrate including a first layer, an insulating layer on the first layer, and a second layer on the insulating layer, a first doped layer on the second layer in the first region and including a first impurity, a second doped layer on the second layer in the second region and including a second impurity different from the first impurity, and an element isolation layer configured to separate the first doped layer from the second doped layer, and in contact with the insulating layer.

Abstract: A semiconductor device includes channels, a gate structure, and a source/drain layer. The channels are disposed at a plurality of levels, respectively, and spaced apart from each other in a vertical direction on an upper surface of a substrate. The gate structure is disposed on the substrate, at least partially surrounds a surface of each of the channels, and extends in a first direction substantially parallel to the upper surface of the substrate. The source/drain layer is disposed at each of opposite sides of the gate structure in a second direction substantially parallel to the upper surface of the substrate and substantially perpendicular to the first direction and is connected to sidewalls of the channels. A length of the gate structure in the second direction changes along the first direction at a first height from the upper surface of the substrate in the vertical direction.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.

Abstract: An integrated circuit (IC) device includes: a fin-type active area protruding from a substrate and extending in a first horizontal direction; a first nanosheet disposed above an upper surface of the fin-type active area with a first separation space therebetween; a second nanosheet disposed above the first nanosheet with a second separation space therebetween; a gate line extending on the substrate in a second horizontal direction intersecting the first horizontal direction, at least a portion of the gate line being disposed in the second separation space; and a bottom insulation structure disposed in the first separation space.