Abstract: Provided are a memory controller with improved data reliability, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes an error correction code (ECC) circuit configured to perform an error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip from among a plurality of memory chips as an indicator chip, monitor an error occurrence in the indicator chip based on a result of the error detection, and output reliability deterioration information indicating that the reliability of the memory device is deteriorated based on a result of the monitoring.

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A memory controller includes an interface and a control module. The interface interfaces with a memory device which includes a plurality of dies that each include a plurality of blocks. The control module groups a plurality of blocks included in different dies and manages the plurality of blocks as a super block. The control module performs scheduling to alternately perform a program on a part of an Nth super block, wherein N is a natural number, and a phased erase on an N+1st super block, and the control module completes the program on the Nth super block and the erase on the Nth super block before the program on the N+1st super block starts.

Abstract: A method of controlling a first memory controller that controls a non-volatile memory device includes: the first memory controller receiving first data and a first physical address from a second memory controller via a first interface of the first memory controller; the first memory controller storing the first data in a non-volatile memory buffer of the first memory controller; and the first memory controller programming the first data stored in the non-volatile memory buffer in a first physical region of the non-volatile memory device corresponding to the first physical address.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: Provided are a memory controller with improved data reliability, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes an error correction code (ECC) circuit configured to perform an error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip from among a plurality of memory chips as an indicator chip, monitor an error occurrence in the indicator chip based on a result of the error detection, and output reliability deterioration information indicating that the reliability of the memory device is deteriorated based on a result of the monitoring.

Abstract: Provided are a memory controller with improved data reliability, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes an error correction code (ECC) circuit configured to perform an error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip from among a plurality of memory chips as an indicator chip, monitor an error occurrence in the indicator chip based on a result of the error detection, and output reliability deterioration information indicating that the reliability of the memory device is deteriorated based on a result of the monitoring.

Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.

Abstract: A method and system of recovering data includes reading reference codewords, which have code correlation with a target codeword, from a memory device when an error-correcting code (ECC) decoding process for a decoder input of the target codeword has failed. A decoder input of a corrected target codeword is generated based on an operation process using the target codeword and the reference codewords. An ECC decoding process is performed again on the decoder input of the corrected target codeword.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of controlling a first memory controller that controls a non-volatile memory device includes: the first memory controller receiving first data and a first physical address from a second memory controller via a first interface of the first memory controller; the first memory controller storing the first data in a non-volatile memory buffer of the first memory controller; and the first memory controller programming the first data stored in the non-volatile memory buffer in a first physical region of the non-volatile memory device corresponding to the first physical address.

Abstract: Provided are a memory controller with improved data reliability, a memory system including the memory controller, and a method of operating the memory controller. The memory controller includes an error correction code (ECC) circuit configured to perform an error detection on a codeword read from a memory device; and a processor configured to set at least one memory chip from among a plurality of memory chips as an indicator chip, monitor an error occurrence in the indicator chip based on a result of the error detection, and output reliability deterioration information indicating that the reliability of the memory device is deteriorated based on a result of the monitoring.

Abstract: A decoder includes a channel mapper configured to generate a plurality of channel reception values based on hard decision information and soft decision information, a strong error detector configured to determine whether a strong error has occurred using a plurality of check node messages and the channel reception values and to correct the channel reception values according to a determination result to produce corrected channel reception values, a variable node unit configured to generate a plurality of variable node messages using the check node messages and the corrected channel reception values, and a check node unit configured to generate the check node messages using the variable node messages. The variable node unit includes a plurality of variable nodes and the check node unit includes a plurality of check nodes.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

Abstract: A redundant array of inexpensive disks (RAID) controller of a RAID storage system that includes one or more storage devices includes an error correction code (ECC) result manager configured to manage information of ECC result indicators when a data chunk that includes one or more ECC data units having an uncorrectable ECC error is read from among a plurality of data chunks dispersively stored in the one or more storage devices, each of the plurality of data chunks including a plurality of ECC data units, the ECC result indicators respectively indicating whether the plurality of ECC data units included in the plurality of data chunks has an uncorrectable ECC error; and an uncorrectable error counter configured to calculate a number of ECC result indicators indicating an uncorrectable ECC error among ECC result indicators corresponding to ECC data units having a same order in each of the plurality of data chunks.

Abstract: A method of operating a memory system includes receiving information data corresponding to a second program unit that is a part of a first program unit and a write request for the information data from a host; generating a codeword by performing error correction code (ECC) encoding on the received information data such that a partial parity bit corresponding to the information data among all parity bits of the codeword is updated; and providing a memory device with the generated codeword and a write command regarding the codeword.

Abstract: A data storage system that provides improved reliability and performance comprises a first memory device including a plurality of first storage components and a first memory controller, the first memory controller controls operation of the first storage components, a second memory device including a plurality of second storage components and a second memory controller, the second memory controller controls operation of the second storage components, a grading device determining grades for each of the first storage components and the second storage components, and a system controller that the location of data based on the grades of the first storage components and the second storage components.