Patents by Inventor Beom-Mo Han
Beom-Mo Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9875788Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: GrantFiled: March 25, 2010Date of Patent: January 23, 2018Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
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Patent number: 9865330Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.Type: GrantFiled: November 4, 2010Date of Patent: January 9, 2018Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Mingu Kang, Hyunkook Park, Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han, Lixin Ge, Zhongze Wang
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Patent number: 9698267Abstract: A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.Type: GrantFiled: July 1, 2014Date of Patent: July 4, 2017Assignee: QUALCOMM IncorporatedInventors: Stanley Seungchul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han
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Patent number: 9337100Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.Type: GrantFiled: June 3, 2009Date of Patent: May 10, 2016Assignee: QUALCOMM IncorporatedInventors: Seung-Chul Song, Beom-Mo Han, Mohamed Hassan Abu-Rahma
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Publication number: 20140313821Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Stanley Seungchul SONG, Mohamed Hassan ABU-RAHMA, Beom-Mo HAN
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Patent number: 8796777Abstract: A method includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.Type: GrantFiled: September 2, 2009Date of Patent: August 5, 2014Assignee: QUALCOMM IncorporatedInventors: Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han
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Patent number: 8558320Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.Type: GrantFiled: December 15, 2009Date of Patent: October 15, 2013Assignee: QUALCOMM IncorporatedInventors: Haining Yang, Chock H. Gan, Zhongze Wang, Beom-Mo Han
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Publication number: 20120113708Abstract: Stable SRAM cells utilizing Independent Gate FinFET architectures provide improvements over conventional SRAM cells in device parameters such as Read Static Noise Margin (RSNM) and Write Noise Margin (WNM). Exemplary SRAM cells comprise a pair of storage nodes, a pair of bit lines, a pair of pull-up devices, a pair of pull-down devices and a pair of pass-gate devices. A first control signal and a second control signal are configured to adjust drive strengths of the pass-gate devices, and a third control signal is configured to adjust drive strengths of the pull-up devices, wherein the first control signal is routed orthogonal to a bit line direction, and the second and third control signals are routed in a direction same as the bit line direction. RSNM and WNM are improved by adjusting drive strengths of the pull-up and pass-gate devices during read and write operations.Type: ApplicationFiled: November 4, 2010Publication date: May 10, 2012Applicants: Industry-Academic Cooperation Foundation, Yonsei University, QUALCOMM IncorporatedInventors: Seong-Ook Jung, Mingu Kang, Hyunkook Park, Seung-Chul Song, Mohamed Abu-Rahma, Beom-Mo Han, Lixin Ge, Zhongze Wang
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Publication number: 20110235406Abstract: A 5 Transistor Static Random Access Memory (5T SRAM) is designed for reduced cell size and immunity to process variation. The 5T SRAM includes a storage element for storing data, wherein the storage element is coupled to a first voltage and a ground voltage. The storage element can include symmetrically sized cross-coupled inverters. A single access transistor controls read and write operations on the storage element. Control logic is configured to generate a value of the first voltage a write operation that is different from the value of the first voltage for a read operation.Type: ApplicationFiled: March 25, 2010Publication date: September 29, 2011Applicants: QUALCOMM INCORPORATED, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Hyunkook Park, Seung-Chul Song, Mohamed Hassan Abu-Rahma, Lixin Ge, Zhongze Wang, Beom-Mo Han
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Publication number: 20110140288Abstract: An integrated circuit device comprising a first elongate structure and a second elongate structure arranged parallel to each other and defining a space therebetween. The integrated circuit device also includes conductive structures distributed in the space between the first and second elongate structures. At least a first one of the conductive structures is placed closer to the first elongate structure than to the second elongate structure. At least a second one of the conductive structures is placed closer to the second elongate structure than to the first elongate structure.Type: ApplicationFiled: December 15, 2009Publication date: June 16, 2011Applicant: QUALCOMM INCORPORATEDInventors: Haining Yang, Chock H. Gan, Zhongze Wang, Beom-Mo Han
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Publication number: 20110051535Abstract: A fin-type device system and method is disclosed. In a particular embodiment, a method of fabricating a transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and forming a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes forming a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent a second BOX layer face of the BOX layer.Type: ApplicationFiled: September 2, 2009Publication date: March 3, 2011Applicant: QUALCOMM INCORPORATEDInventors: Seung-Chul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han
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Publication number: 20100308408Abstract: An apparatus and method to fabricate an electronic device is disclosed. In a particular embodiment, an apparatus includes a template having an imprint surface. The imprint surface includes a first region having a first pattern adapted to fabricate a fin field effect transistor (FinFET) device and a second region having a second pattern adapted to fabricate a planar electronic device.Type: ApplicationFiled: June 3, 2009Publication date: December 9, 2010Applicant: QUALCOMM INCORPORATEDInventors: Seung-Chul Song, Beom-Mo Han, Mohamed Hassan Abu-Rahma
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Patent number: 7829951Abstract: A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.Type: GrantFiled: November 6, 2008Date of Patent: November 9, 2010Assignee: QUALCOMM IncorporatedInventors: Seung-Chul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han
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Publication number: 20100109086Abstract: A method of fabricating a semiconductor using a fin field effect transistor (FINFET) is disclosed. In a particular embodiment, a method includes depositing, on a silicon substrate, a first dummy structure having a first sidewall and a second sidewall separated by a first width. The method also includes depositing, on the silicon substrate, a second dummy structure concurrently with depositing the first dummy structure. The second dummy structure has a third sidewall and a fourth sidewall that are separated by a second width. The second width is substantially greater than the first width. The first dummy structure is used to form a first pair of fins separated by approximately the first width. The second dummy structure is used to form a second pair of fins separated by approximately the second width.Type: ApplicationFiled: November 6, 2008Publication date: May 6, 2010Applicant: QUALCOMM INCORPORATEDInventors: Seung-Chul Song, Mohamed Hassan Abu-Rahma, Beom-Mo Han