Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory cells and a memory controller. The memory controller may be configured to control the memory device to generate dummy data based on write data, when a size of the write data is less than a preset size, and to store program data including the write data and the dummy data in selected memory cells among the plurality of memory cells.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system writes, when performing the sudden power-off recovery operation, a plurality of target segments which are segments most recently written to each of the plurality of open memory blocks among the plurality of memory blocks to a target memory block among the plurality of memory blocks.

Abstract: A memory controller and a method of operating the same may provide recovery from a Sudden Power-Off (SPO). The memory controller may control a memory device including a plurality of memory blocks, each memory block having a plurality of pages. The memory controller may include a dummy program controller configured to, after an SPO has occurred while a program operation was being performed on a page of the memory device, control a dummy program operation for recovering from the SPO; a parity data controller configured to control resetting and generation of parity data for chipkill decoding based on pages on which the dummy program operation is determined to be performed; and a valid data controller configured to control movement of valid data based on a number of pages on which the dummy program operation is to be performed.

Abstract: Systems and methods that relate to memory devices are disclosed. In some implementations, a memory system includes a first data storage device and a second data storage device. Each of the first and second data storage devices includes a plurality of memory blocks, each memory block including a plurality of memory cells each operable to store one or more data bits, and page buffers that cache data to be written to the memory blocks or read from the plurality of memory blocks on a page basis, and a controller including a cache memory configured to temporarily store first data, and configured to move the first data from a portion of the cache memory to one or more of the page buffers of the first data storage device and allocate the portion of the cache memory as a temporary buffer for storing data.

Abstract: Embodiments of the present disclosure relate to a memory system and an operating method of the memory system. According to embodiments of the present disclosure, a memory system writes, when performing the sudden power-off recovery operation, a plurality of target segments which are segments most recently written to each of the plurality of open memory blocks among the plurality of memory blocks to a target memory block among the plurality of memory blocks.

Abstract: A memory controller and a method of operating the same may provide recovery from a Sudden Power-Off (SPO). The memory controller may control a memory device including a plurality of memory blocks, each memory block having a plurality of pages. The memory controller may include a dummy program controller configured to, after an SPO has occurred while a program operation was being performed on a page of the memory device, control a dummy program operation for recovering from the SPO; a parity data controller configured to control resetting and generation of parity data for chipkill decoding based on pages on which the dummy program operation is determined to be performed; and a valid data controller configured to control movement of valid data based on a number of pages on which the dummy program operation is to be performed.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include a memory device including a plurality of memory cells and a memory controller. The memory controller may be configured to control the memory device to generate dummy data based on write data, when a size of the write data is less than a preset size, and to store program data including the write data and the dummy data in selected memory cells among the plurality of memory cells.

Abstract: A memory system includes a nonvolatile memory device; and a controller configured to receive an operation command for a target logical address from a host device, and control the nonvolatile memory device in response to the operation command, wherein the controller determines a target logical address range including the target logical address among a plurality of logical address ranges, and determines whether the target logical address has a sequential attribute, based on a target count corresponding to the target logical address range among counts corresponding to the plurality of logical address ranges.

Abstract: A controller may include a first processor suitable for sequentially storing commands provided from a host into one of first and second mailboxes of a memory according to types of the commands; and a second processor suitable for serving the commands stored in the first and second mailboxes, wherein, when provided from the host is a first command corresponding to the same logical address as a second command stored in the second mailbox, the first and second commands being of different types, the first processor stores the first command into the first mailbox and stores into the memory a priority information representing the second command having a higher processing priority to the first command, and wherein the second processor serves the commands stored in the first mailbox and the second mailbox by referring to the priority information.

Abstract: A memory system may include: a nonvolatile memory device including a memory cell array and a page buffer coupled to the memory cell array; and a controller configured to interface with the nonvolatile memory device, wherein the controller moves descriptors on a cache command from a command queue to a cache queue, the cache command being transferred to the nonvolatile memory device, and selectively moves the descriptors moved to the cache queue to a response queue.

Abstract: A memory system includes a nonvolatile memory device; and a controller configured to receive an operation command for a target logical address from a host device, and control the nonvolatile memory device in response to the operation command, wherein the controller determines a target logical address range including the target logical address among a plurality of logical address ranges, and determines whether the target logical address has a sequential attribute, based on a target count corresponding to the target logical address range among counts corresponding to the plurality of logical address ranges.

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks each of which includes a plurality of pages; a volatile memory device configured to temporarily store data to be transmitted between a host and the nonvolatile memory device; and a controller configured to enter an exclusive mode in response to a request of the host, a result of checking a state of the nonvolatile memory device, or performing a merge operation on the nonvolatile memory device, exclusively use the volatile memory device to perform the merge operation during an entry period of the exclusive mode, and exit the exclusive mode in response to completing the performing of the merge operation.

Abstract: A data storage device includes a nonvolatile memory device; and a controller including a plurality of buffers and suitable for, when a program fail occurs in the nonvolatile memory device, transmitting exchange data stored in an optional exchange buffer among the plurality of buffers, to the nonvolatile memory device, storing and updating, in the exchange buffer, failed program data received from the nonvolatile memory device, and transmitting the updated program data to the nonvolatile memory device.

Abstract: A memory system may include: a nonvolatile memory device, a volatile memory device, a free exclusive mode flag configured to correspond to an entrance/exit state of a free exclusive mode, a host controller configured to process a first operation with the host and delay a process of the first operation in an entrance period of the free exclusive mode which is knowable by checking a value of the free exclusive flag, and a memory controller configured to process a second operation with the nonvolatile memory device, set the value of the free exclusive flag in response to a result of checking a state of the nonvolatile memory device, and exclusively use the volatile memory device so as to process a merge operation in the second operation in the entrance period of the free exclusive mode that is knowable by checking the value of the free exclusive flag.

Abstract: A memory system may include: a nonvolatile memory comprising a plurality of memory blocks, each including a plurality of pages; a volatile memory suitable for temporarily storing data transferred between a host and the nonvolatile memory; and a controller suitable for determining whether to start or end an automatic exclusive mode in response to a request from the host or a result obtained by checking a state of the nonvolatile memory, repeatedly entering into, or exiting from, the automatic exclusive mode in each set cycle when the automatic exclusive mode is started, and exclusively using the volatile memory to perform a merge operation on the nonvolatile memory during an entry period of the automatic exclusive mode in each set cycle.

Abstract: A memory system may include: a nonvolatile memory device comprising a plurality of memory blocks each of which includes a plurality of pages; a volatile memory device configured to temporarily store data to be transmitted between a host and the nonvolatile memory device; and a controller configured to enter an exclusive mode in response to a request of the host, a result of checking a state of the nonvolatile memory device, or performing a merge operation on the nonvolatile memory device, exclusively use the volatile memory device to perform the merge operation during an entry period of the exclusive mode, and exit the exclusive mode in response to completing the performing of the merge operation.

Abstract: A memory system may include: a nonvolatile memory device including a memory cell array and a page buffer coupled to the memory cell array; and a controller configured to interface with the nonvolatile memory device, wherein the controller moves descriptors on a cache command from a command queue to a cache queue, the cache command being transferred to the nonvolatile memory device, and selectively moves the descriptors moved to the cache queue to a response queue.

Abstract: A data storage device includes a nonvolatile memory device; and a controller including a plurality of buffers and suitable for, when a program fail occurs in the nonvolatile memory device, transmitting exchange data stored in an optional exchange buffer among the plurality of buffers, to the nonvolatile memory device, storing and updating, in the exchange buffer, failed program data received from the nonvolatile memory device, and transmitting the updated program data to the nonvolatile memory device.

Abstract: A controller may include a first processor suitable for sequentially storing commands provided from a host into one of first and second mailboxes of a memory according to types of the commands; and a second processor suitable for serving the commands stored in the first and second mailboxes, wherein, when provided from the host is a first command corresponding to the same logical address as a second command stored in the second mailbox, the first and second commands being of different types, the first processor stores the first command into the first mailbox and stores into the memory a priority information representing the second command having a higher processing priority to the first command, and wherein the second processor serves the commands stored in the first mailbox and the second mailbox by referring to the priority information.

Abstract: A controller includes a memory including one or more command queues for queuing commands according to their type, each command queue operating on a first-in-first-out (FIFO) scheme a first processor suitable for queueing a plurality of commands into a corresponding one among the command queues, and for storing in the memory first and second information about the queued commands; and a second processor suitable for processing the queued command of the respective command queues according to the first and second information of the queued commands.