Abstract: A method of communication to a semiconductor device includes: transmitting a sampling clock signal from a first semiconductor device to a second semiconductor device; transmitting a training signal from the first semiconductor device to the second semiconductor device while transmitting of the sampling clock signal, the training signal comprising plural test patterns sent sequentially to the second semiconductor device, phases of at least some of the test patterns being adjusted to be different from each other during transmitting of the training signal; receiving first information from the second semiconductor device over a first signal line, the first signal line separate from a data bus connected between the first semiconductor device and the second semiconductor device; and transmitting a data signal over the data bus while transmitting the sampling clock signal, the data signal sent at a timing with respect to the sampling clock signal responsive to the received first information.

Abstract: A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

Abstract: In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state.

Abstract: A power-down method for a system including a plurality of volatile memory devices is disclosed. The method includes providing some of the plurality of volatile memory devices or some memory regions of the volatile memory devices to operate in a self-refresh mode, thereby increasing a rebooting operation speed and reducing power consumption.

Abstract: A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

Abstract: A memory device includes a clock receiving block, a data transceiver block, a phase detection block, and a phase information transmitter. The clock receiving block is configured to receive a clock signal from a memory controller through a clock signal line and generate a data sampling clock signal and an edge sampling clock signal. The data transceiver block is configured to receive a data signal from the memory controller through a data signal line. The phase detection block is configured to generate phase information in response to the data sampling clock signal, the edge sampling clock signal and the data signal. The phase information transmitter is configured to transmit the phase information to the memory controller through a phase information signal line that is separate from the data signal line.

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided.

Abstract: In one embodiment, a method of performing data training in a system including a memory controller and at least a first memory device including a group of memory banks is disclosed. The method includes providing a plurality of enabling states for the group of memory banks, wherein each enabling state is different and for each enabling state a set of the memory banks of the group is enabled and any remaining of the memory banks of the group are not enabled. The method further includes performing a first data training procedure that includes a series of first data training operations for the first memory device, each data training operation being performed for a different one of the plurality of enabling states, generating a noise profile based on the series of first data training operations, statistically analyzing the noise profile to select a reference enabling state of the group of memory banks, and performing a second data training procedure for the first memory device using the reference enabling state.

Abstract: A memory system includes an error detection circuit having an error counter. When a bit error rate (BER) determined by the error counter exceeds a reference BER, the memory system reduces the BER by adjusting its operating speed or operating voltage, re-performing data training or impedance matching, or by adjusting a data swing width. Accordingly, a method of controlling a bit error rate may be performed, and a system hang is prevented.

Abstract: A power-down method for a system including a plurality of volatile memory devices is disclosed. The method includes providing some of the plurality of volatile memory devices or some memory regions of the volatile memory devices to operate in a self-refresh mode, thereby increasing a rebooting operation speed and reducing power consumption.

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided.

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided.

Abstract: A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.

Abstract: A semiconductor device, a parallel interface system and methods thereof are provided.

Abstract: A level shifting circuit and method that reduce leakage current are provided. The level shifting circuit includes: a logic circuit including a plurality of MOSFETs (metal-oxide-semiconductor field effect transistors) connected in series between an output terminal and a source, receiving an input signal having a first logic level and a second logic level, changing the input signal to a signal having a first logic level and a third logic level in response to a feedback signal supplied to one of the MOSFETs, and outputting the changed signal as an output signal; and a feedback circuit generating the feedback signal in response to the output signal.