Patents by Inventor Beom-Yong Kim

Beom-Yong Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240088257
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Application
    Filed: November 14, 2023
    Publication date: March 14, 2024
    Inventor: Beom-Yong KIM
  • Patent number: 11855172
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Grant
    Filed: May 10, 2022
    Date of Patent: December 26, 2023
    Assignee: SK hynix Inc.
    Inventor: Beom-Yong Kim
  • Publication number: 20220271143
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Application
    Filed: May 10, 2022
    Publication date: August 25, 2022
    Inventor: Beom-Yong KIM
  • Patent number: 11342437
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: May 24, 2022
    Assignee: SK hynix Inc.
    Inventor: Beom-Yong Kim
  • Patent number: 11094778
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Grant
    Filed: May 19, 2020
    Date of Patent: August 17, 2021
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Deok-Sin Kil, Hee-Young Jeon
  • Patent number: 11043533
    Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.
    Type: Grant
    Filed: June 27, 2019
    Date of Patent: June 22, 2021
    Assignee: SK hynix Inc.
    Inventors: Beom Yong Kim, Soo Gil Kim
  • Patent number: 10910383
    Abstract: A method for fabricating a semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.
    Type: Grant
    Filed: April 27, 2020
    Date of Patent: February 2, 2021
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Hun Lee, Deok-Sin Kil
  • Publication number: 20200279906
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Application
    Filed: May 19, 2020
    Publication date: September 3, 2020
    Inventors: Beom-Yong KIM, Deok-Sin KIL, Hee-Young JEON
  • Publication number: 20200258888
    Abstract: A method for fabricating a semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.
    Type: Application
    Filed: April 27, 2020
    Publication date: August 13, 2020
    Inventors: Beom-Yong KIM, Hun LEE, Deok-Sin KIL
  • Patent number: 10700162
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Grant
    Filed: May 21, 2019
    Date of Patent: June 30, 2020
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Deok-Sin Kil, Hee-Young Jeon
  • Patent number: 10672772
    Abstract: A method for fabricating semiconductor device includes: forming a bottom electrode of a high aspect ratio; forming an interface layer by sequentially performing a first plasma process and a second plasma process onto a surface of the bottom electrode; forming a dielectric layer over the interface layer; and forming a top electrode over the dielectric layer.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: June 2, 2020
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Hun Lee, Deok-Sin Kil
  • Publication number: 20200168717
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Application
    Filed: February 3, 2020
    Publication date: May 28, 2020
    Inventor: Beom-Yong KIM
  • Patent number: 10593777
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Grant
    Filed: December 27, 2018
    Date of Patent: March 17, 2020
    Assignee: SK hynix Inc.
    Inventor: Beom-Yong Kim
  • Publication number: 20200020780
    Abstract: A semiconductor layer stack includes a first conductive layer, a dielectric layer including a high-k material, which is formed on the first conductive layer, a second conductive layer formed on the dielectric layer, and an interface control layer formed between the dielectric layer and the second conductive layer and including a leakage blocking material, a dopant material, a high bandgap material and a high work function material.
    Type: Application
    Filed: December 27, 2018
    Publication date: January 16, 2020
    Inventor: Beom-Yong KIM
  • Publication number: 20190319070
    Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.
    Type: Application
    Filed: June 27, 2019
    Publication date: October 17, 2019
    Inventors: Beom Yong KIM, Soo Gil KIM
  • Publication number: 20190273129
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Application
    Filed: May 21, 2019
    Publication date: September 5, 2019
    Inventors: Beom-Yong KIM, Deok-Sin KIL, Hee-Young JEON
  • Patent number: 10381407
    Abstract: A switch includes a first electrode layer, a second electrode layer disposed over the first electrode layer, and a selecting element layer interposed between the first electrode layer and the second electrode layer. The selecting element layer includes a gas region in which a current flows or does not flow according to a voltage applied to the switch. When the current flows, the switch is in an on-state, and, when the current does not flow, the switch is in an off-state.
    Type: Grant
    Filed: February 14, 2017
    Date of Patent: August 13, 2019
    Assignee: SK hynix Inc.
    Inventors: Beom Yong Kim, Soo Gil Kim
  • Patent number: 10347711
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Grant
    Filed: June 7, 2018
    Date of Patent: July 9, 2019
    Assignee: SK hynix Inc.
    Inventors: Beom-Yong Kim, Deok-Sin Kil, Hee-Young Jeon
  • Publication number: 20190165087
    Abstract: A method for fabricating a capacitor includes: forming a bottom electrode; forming a dielectric layer on the bottom electrode; forming a metal oxide layer including a metal having a high electronegativity on the dielectric layer; forming a sacrificial layer on the metal oxide layer to reduce the metal oxide layer to a metal layer; and forming a top electrode on the sacrificial layer to convert the reduced metal layer into a high work function interface layer.
    Type: Application
    Filed: June 7, 2018
    Publication date: May 30, 2019
    Inventors: Beom-Yong KIM, Deok-Sin KIL, Hee-Young JEON
  • Patent number: 10224369
    Abstract: A threshold switching device may include: a first electrode layer; a second electrode layer; a first insulating layer interposed between the first and second electrode layers, and provided adjacent to the first electrode layer; and a second insulating layer interposed between the first and second electrode layers, and provided adjacent to the second electrode layer, wherein the first and second insulating layers contain a plurality of neutral defects, a concentration of the plurality of neutral defects being at a maximum along a first interface between the first insulating layer and the second insulating layer, and wherein the threshold switching device has an ON or OFF state according to whether electrons are ejected from the plurality of neutral defects.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: March 5, 2019
    Assignee: SK HYNIX INC.
    Inventors: Jong-Chul Lee, Beom-Yong Kim, Hyung-Dong Lee