Abstract: A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

Abstract: An apparatus and a method for setting a routing path in System-on-a-Chip (SoC) having an n×n net topology-based structure comprising a plurality of intellectual properties (IPs), each with a unique address, and a plurality of switches forming one-to-one correspondence to the IPs, to transmit and receive data between the IPs by using at least one of the switches. Accordingly, an orthogonal code having orthogonality is assigned according to the direction of transmission of each data (that is, output port). Then, an output port where the data is transmitted is determined, and the data is spread based on an orthogonal code assigned to the output ports of the at least one of the switches.

Abstract: An apparatus and a method for setting a routing path in System-on-a-Chip (SoC) having an n×n net topology-based structure comprising a plurality of intellectual properties (IPs), each with a unique address, and a plurality of switches forming one-to-one correspondence to the IPs, to transmit and receive data between the IPs by using at least one of the switches. Accordingly, an orthogonal code having orthogonality is assigned according to the direction of transmission of each data (that is, output port). Then, an output port where the data is transmitted is determined, and the data is spread based on an orthogonal code assigned to the output ports of the at least one of the switches.

Abstract: A method of establishing a path between routers in a system-on-chip (SoC) of n×n mesh topology structure having a plurality of intellectual properties (IPs) each with a unique address and routers corresponding to each of the IPs respectively, including: receiving a routing packet including a hop counter, and updating address information and information of a stored routing table; establishing a path to at least one neighboring router using the updated routing table upon a request to establish the path; and delivering data by using the established path.

Abstract: A GALS-based network-on-chip (NoC) includes a plurality of asynchronous first-in first-out (FIFO) input buffers connected to a plurality of IPs that asynchronously receive data; a plurality of asynchronous FIFO output buffers connected to the plurality of IPs asynchronously output data; and a router for forwarding data input to the plurality of asynchronous FIFO input buffers, to an asynchronous FIFO output buffer, among the plurality of asynchronous FIFO output buffers, which is connected to an IP to which the data is destined. Accordingly, the system-on-chip (SoC) adopting the GALS design scheme can transfer data via the NoC between the IPs which are in time zones having different clocks in the centralized switching system, thereby avoiding the need for a point-to-point system.

Abstract: An input buffer device and control method of the input buffer device. The input buffer device includes a virtual output queuing (VOQ) buffering section which has a plurality of VOQ buffers. The input buffer device stores data which is input to an input port to a VOQ buffer corresponding to an intended output port of the data among the plurality of VOQ buffers. A shared buffering section is provided which stores the data when a VOQ buffer corresponding to the intended output port of the data is full of data. The stored data is forwarded to the VOQ buffer when the VOQ buffer is empty. Accordingly, the input buffer device can more efficiently process the data by use of the fixed-length FIFO buffers and the shared buffer.

Abstract: A Network-on-Chip (NoC) system employing an Advanced extensible Interface (AXI) protocol is provided. The NoC includes an NoC router which classifies data transmitted from a plurality of AXI Intellectual Properties (IPs) according to a destination AXI IP, and a network interface (NI) which processes data from the NoC router and provides the processed data to the destination IP. One of the NoC router and the NI includes a plurality of buffers which store data provided from each of the AXI IPs and classified according to each of the AXI IPs, and an interleaving manager which selects buffers, from which data is retrieved, among the plurality of buffers according to an interleaving acceptance capability which is a number of interleaving data that can be accepted by the destination AXI IP.

Abstract: A network on chip system employing an advanced extensible interface protocol is provided. The network on chip system employing the advanced extensible interface protocol includes a plurality of intellectual properties (IPs) which are installed in a chip and read and write data; a router which is connected to the plurality of IPs and transmits data; and a plurality of network interfaces (NIs), each NI corresponding to a respective one of the plurality of IPs and installed between the respective IP and the router, wherein each NI is configured to process data transmitted between the respective IP and the router and to divide data provided from the respective IP into at least one packet.

Abstract: A switching device of NoC (Networks on Chip) system and a scheduling method thereof. The switching device has a switching part having a plurality of input ports and a plurality of output ports, and a scheduler for setting a transmission route between the input ports and the output ports, determining the length of code based on the number of input ports having the data among the plurality of input ports, and assigning a predetermined code of the determined code length to the input port and the output port corresponding to the set transmission route. Because the code length is adjustably varied according to the number of transmission packets, switch performance improves.

Abstract: System-on-a-chip using a CDMA bus and data transmission method therefor. The system-on-a-chip has plural IP-cores dividing into at least one group according to a predetermined reference; and at least one arbiter connected to the IP-cores belonging to the at least one group, receiving a unique ID of a reception-side IP-core receiving data from a transmission-side IP-core sending the data, and sending the transmission-side IP-core a code word assigned to the reception-side IP-core corresponding to the received unique ID, thereby reducing the length of the code word assigned to the IP-cores.