Abstract: Gallium nitride (GaN) three-dimensional integrated circuit technology is described. In an example, an integrated circuit structure includes a layer including gallium and nitrogen, a plurality of gate structures over the layer including gallium and nitrogen, a source region on a first side of the plurality of gate structures, a drain region on a second side of the plurality of gate structures, the second side opposite the first side, and a drain field plate above the drain region wherein the drain field plate is coupled to the source region. In another example, a semiconductor package includes a package substrate. A first integrated circuit (IC) die is coupled to the package substrate. The first IC die includes a GaN device layer and a Si-based CMOS layer.

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Abstract: Provided are an organic salt represented by Formula 1, a resist composition including the same, and a method of forming a pattern by using the same: A11+B11???Formula 1 wherein, in Formula 1, A11+ is represented by Formula 1A, and B11? is represented by Formula 1B, wherein descriptions of R11 to R13, L21, L22, a21, a22, R21, R22, Rf, b22, c11 and n11 in Formulae 1A and 1B are provided herein.

Abstract: Provided are a resist composition and a pattern forming method using the same. The resist composition includes a polymer including a first repeating unit repeating unit Formula 1, a photoacid generator, and an organic solvent. In Formula 1, L11 to L13, a11 to a13, A11 to A13, R11 to R14, b12 to b14, and p are the same as described in the detailed description.

Abstract: Provided are a photoreactive polymer compound including a first repeating unit represented by Formula 1 below, a photoresist composition including the same, and a method of forming a pattern by using the photoresist composition: A description of Formula 1 is provided herein.

Abstract: An electronic package comprises, a package substrate, and a magnetic block, where the magnetic block passes through the package substrate. the electronic package further comprises a fluidic path from an inlet to the package substrate to an outlet of the package substrate. The electronic package further comprises a conductive winding in the package substrate, where the conductive winding wraps around the magnetic block, and where the conductive winding is tubular and the fluidic path passes through the conductive winding.

Abstract: An integrated circuit assembly may be fabricated having an electronic substrate, an integrated circuit device having a first surface, an opposing second surface, at least one side extending between the first surface and the second surface, and at least one through-substrate via extending into the integrated circuit device from the second surface, wherein the first surface of the integrated circuit device is electrically attached to the electronic substrate; and at least one power delivery route electrically attached to the second surface of the integrated circuit device and to the electronic substrate, wherein the at least one power delivery route is conformal to the side of the integrated circuit device and the first surface of the electronic substrate.

Abstract: Embodiments disclosed herein include two stage voltage regulators for electronic systems. In an embodiment, a voltage regulator comprises a switched capacitor voltage regulator (SCVR). In an embodiment, the SCVR receives a first voltage as an input and outputs a plurality of SCVR output voltages. In an embodiment, the voltage regulator further comprises a low-dropout (LDO) regulator. In an embodiment, the LDO regulator receives one or more of the plurality of SCVR output voltages as LDO input voltages, and where the LDO regulator outputs a second voltage.

Abstract: An example air conditioner may include a compressor configured to compress a refrigerant; an indoor heat exchanger configured to perform heat exchange between the refrigerant and indoor air; a temperature sensor configured to measure an indoor temperature and an indoor heat exchanger temperature; an input device configured to receive a target temperature and target humidity from a user; and at least one processor configured to determine an adjustment value of an operating frequency of the compressor based on a temperature difference between the target temperature and the indoor temperature, and change the determined adjustment value of the operating frequency based on the target humidity and the indoor heat exchanger temperature.

Abstract: An air conditioner may include: a compressor; a flow path switching valve; a first flow path connecting an outlet of the compressor to the flow path switching valve; a first heat exchanger; a second flow path connecting the first heat exchanger to the flow path switching valve; a first refrigerant port fluidly connected to an indoor unit; a third flow path extending from the first heat exchanger to the first refrigerant port; a sub-cooler provided on the third flow path; a first expansion valve provided between the first heat exchanger and the sub-cooler on the third flow path; a second expansion valve provided between the sub-cooler and the first refrigerant port on the third flow path; a fourth flow path branched from a branch point of the third flow path, passing through the sub-cooler, and extending to an inlet of the compressor; a third expansion valve provided between the sub-cooler and the branch point on the fourth flow path; a second refrigerant port fluidly connected to the indoor unit; a fifth flow

Abstract: A microelectronic structure, a semiconductor package, an IC device assembly, and a method. The structure includes a core layer including an electrically non-conductive material; electrically conductive through core vias (TCVs) through the core layer; a dielectric layer on the core layer with electrically conductive structures extending therethrough and electrically coupled to the TCVs; and a magnetic inductor (MI) within at least one of the core layer or the build-up layer and including an antiferromagnetic (AF) structure. The AF structure includes a first ferromagnetic (FM) layer; an exchange coupling (EC) layer on the first FM layer and including a non-magnetic metal material; a second FM layer on the EC layer, the EC layer between the first FM layer and the second FM layer; and a pinning (P) layer including manganese and at least one of platinum or iridium, the second FM layer between the EC layer and the P layer.

Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.

Abstract: An electronic device includes a substrate including a core layer; buildup layers on a first surface of the core layer, the buildup layers including first contact pads below the top surface of the buildup layers and second contact pads on a top surface of the buildup layers; and a discrete passive electronic component disposed in the buildup layers, the discrete component including bottom contact pads on a bottom surface of the discrete component and top contact pads on a top surface of the discrete component. The bottom contact pads of the discrete component are bonded to the first contacts pads of the buildup layers and the top contact pads of the discrete component are electrically connected to the second contact pads of the buildup layers.

Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.

Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.

Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a via opening is formed through a thickness of the substrate, and a first layer is over sidewalls of the via opening. In an embodiment, the first layer comprises a magnetic material. In an embodiment, a second layer is over the first layer, where the second layer is an insulator. In an embodiment, a third layer fills the via opening, where the third layer is a conductor.

Abstract: The present disclosure relates to a composition for gene manipulation for artificially manipulating a blood coagulation inhibitory gene present in the genome of a cell to regulate a blood coagulation system. More particularly, the present invention relates to a composition for gene manipulation, which includes a guide nucleic acid capable of targeting a blood coagulation inhibitory gene, and an editor protein. Also, the present invention relates to a method of treating or improving coagulopathy using the composition for gene manipulation for artificially manipulating a blood coagulation inhibitory gene.

Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.

Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.