Patents by Inventor Beomseok Choi

Beomseok Choi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240170212
    Abstract: A capacitor, a semiconductor device, and an electronic apparatus including the semiconductor device are disclosed. The capacitor includes a first electrode; a second electrode disposed apart from the first electrode; a dielectric film between the first electrode and the second electrode; and a leakage current reducing layer provided on the dielectric film between the first electrode and the second electrode and including MxAlyOz.
    Type: Application
    Filed: July 11, 2023
    Publication date: May 23, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jeonggyu SONG, Eunae CHO, Narae HAN, Beomseok KIM, Cheheung KIM, Jooho LEE, Wonsik CHOI
  • Publication number: 20240124635
    Abstract: Provided are a polymer, a resist composition including the same, and a method of forming a pattern using the resist composition, the polymer including one or more of a first repeating unit represented by Formula 1 and a second repeating unit represented by Formula 2, and free of a repeating unit of which a structure changes by an acid: In Formulae 1 and 2, R11 to R16, b12, X?, R21 to R24, b22, and Y are as described in the specification.
    Type: Application
    Filed: February 6, 2023
    Publication date: April 18, 2024
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Minsang KIM, Haengdeog KOH, Yoonhyun KWAK, Beomseok KIM, Chanjae AHN, Jungha CHAE, Sungwon CHOI
  • Publication number: 20240114622
    Abstract: An electronic device includes a substrate including a core layer; a cavity formed in the core layer, wherein the cavity includes sidewalls plated with a conductive material; a prefabricated passive electronic component disposed in the cavity; and a cavity sidewall connection providing electrical continuity from the plated cavity sidewalls to a first surface of the substrate and to a second surface of the substrate.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Kristof Darmawikarta, Srinivas Venkata Ramanuja Pietambaram, Tarek A. Ibrahim, Cary Kuliasha, Siddharth K. Alur, Jung Kyu Han, Beomseok Choi, Russell K. Mortensen, Andrew Collins, Haobo Chen, Brandon C. Marin
  • Publication number: 20240113000
    Abstract: An electronic device includes a substrate including a core layer; buildup layers on a first surface of the core layer, the buildup layers including first contact pads below the top surface of the buildup layers and second contact pads on a top surface of the buildup layers; and a discrete passive electronic component disposed in the buildup layers, the discrete component including bottom contact pads on a bottom surface of the discrete component and top contact pads on a top surface of the discrete component. The bottom contact pads of the discrete component are bonded to the first contacts pads of the buildup layers and the top contact pads of the discrete component are electrically connected to the second contact pads of the buildup layers.
    Type: Application
    Filed: September 29, 2022
    Publication date: April 4, 2024
    Inventors: Kristof Darmawikarta, Ravindranath V. Mahajan, Srinivas Venkata Ramanuja Pietambaram, Gang Duan, Beomseok Choi
  • Publication number: 20240063183
    Abstract: Embodiments of a microelectronic assembly comprise: a plurality of layers of monolithic wafers and disaggregated integrated circuit (IC) dies, adjacent layers being coupled together by first interconnects having a pitch less than 10 micrometers between adjacent first interconnects, the disaggregated IC dies arranged with portions of the monolithic wafers into modular sub-assemblies; and a package substrate coupled to the modular sub-assemblies by second interconnects having a pitch greater than 10 micrometers between adjacent second interconnects. The disaggregated IC dies are surrounded laterally by a dielectric material, and the disaggregated IC dies are arranged with portions of the monolithic wafers such that a voltage regulator circuit in a first layer of the plurality of layers, a compute circuit in a second layer of the plurality of layers, and a memory circuit in a third layer of the plurality of layers are conductively coupled together in an intra-modular power delivery circuitry.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel A. Elsherbini, Kaladhar Radhakrishnan, Anne Augustine, Beomseok Choi, Kimin Jun, Omkar G. Karhade, Shawna M. Liff, Julien Sebot, Johanna M. Swan, Krishna Vasanth Valavala
  • Publication number: 20240063133
    Abstract: A multichip composite device includes on- and off-die metallization layers, inorganic dielectric material, and stacked hybrid-bonded dies. On-die metallization layers may be thinner than off-die metallization layers. The multichip composite device may include a structural substrate. Off-die metallization layers may be above and below the stacked hybrid-bonded dies. A substrate may couple the multichip composite device to a power supply in a multichip system. Forming a multichip composite device includes hybrid bonding dies and forming inorganic dielectric material.
    Type: Application
    Filed: August 19, 2022
    Publication date: February 22, 2024
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Beomseok Choi, Feras Eid, Omkar Karhade, Shawna Liff
  • Patent number: 11710720
    Abstract: A semiconductor package is provided, which includes a first die and a second die. The first die includes a first section of a power converter, and the second die includes a second section of the power converter. The power converter may include a plurality of switches, and a Power Management (PM) circuitry to control operation of the power converter by controlling switching of the plurality of switches. The PM circuitry may include a first part and a second part. The first section of the power converter in the first die may include the first part of the PM circuitry, and the second section of the power converter in the second die may include the second part of the PM circuitry.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: July 25, 2023
    Assignee: Intel Corporation
    Inventors: Beomseok Choi, Siddharth Kulasekaran, Kaladhar Radhakrishnan
  • Publication number: 20230207492
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a via opening is formed through a thickness of the substrate, and a first layer is over sidewalls of the via opening. In an embodiment, the first layer comprises a magnetic material. In an embodiment, a second layer is over the first layer, where the second layer is an insulator. In an embodiment, a third layer fills the via opening, where the third layer is a conductor.
    Type: Application
    Filed: December 23, 2021
    Publication date: June 29, 2023
    Inventors: Aleksandar ALEKSOV, Georgios C. DOGIAMIS, Neelam PRABHU GAUNKAR, Telesphor KAMGAING, Veronica STRONG, Brandon RAWLINGS, Robert MONGRAIN, Beomseok CHOI
  • Publication number: 20230190889
    Abstract: The present disclosure relates to a composition for gene manipulation for artificially manipulating a blood coagulation inhibitory gene present in the genome of a cell to regulate a blood coagulation system. More particularly, the present invention relates to a composition for gene manipulation, which includes a guide nucleic acid capable of targeting a blood coagulation inhibitory gene, and an editor protein. Also, the present invention relates to a method of treating or improving coagulopathy using the composition for gene manipulation for artificially manipulating a blood coagulation inhibitory gene.
    Type: Application
    Filed: January 20, 2023
    Publication date: June 22, 2023
    Inventors: DONG WOO SONG, BEOMSEOK CHOI, HYEKYUNG OH, NANYEONG GO, HYERIM LEE, KYU JUN LEE, UN GI KIM, JAEYOUNG LEE, JUNG MIN LEE
  • Publication number: 20230095063
    Abstract: In one embodiment, an apparatus includes a first die with voltage regulator circuitry and a second die with logic circuitry. The apparatus further includes an inductor, a capacitor, and a conformal power delivery structure on the top side of the apparatus, where the voltage regulator circuitry is connected to the logic circuitry through the inductor, the capacitor, and the conformal power delivery structure. The conformal power delivery structure includes a first electrically conductive layer defining one or more recesses, a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer, and a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Beomseok Choi, William J. Lambert, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini, Henning Braunisch, Stephen Morein, Aleksandar Aleksov, Feras Eid
  • Publication number: 20230095654
    Abstract: In one embodiment, a conformal power delivery structure includes a first electrically conductive layer comprising metal. The first electrically conductive layer defines one or more recesses, and the conformal power delivery structure also includes a second electrically conductive layer comprising metal that is at least partially within the recesses of the first electrically conductive layer. The second electrically conductive layer has a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure further includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Inventors: Adel Elsherbini, Feras Eid, Stephen Morein, Krishna Bharath, Henning Braunisch, Beomseok Choi, Brandon M. Rawlings, Thomas L. Sounart, Johanna Swan, Yoshihiro Tomita, Aleksandar Aleksov
  • Publication number: 20230095608
    Abstract: A embedded passive structure, a microelectronic system, and an integrated circuit device assembly, and a method of forming the embedded passive structure. The embedded passive structure includes a base layer; a passive device attached to the base layer; a first power plane comprising metal and adjacent an upper surface of the base layer, the first power plane having a portion electrically coupled to a terminal of the passive device, wherein an upper surface of a combination of the first power plane and the passive device defines a recess; a second power plane comprising metal, the second power plane at least partially within the recess and having a lower surface that conforms with the upper surface of the combination; and a liner including a dielectric layer between the first power plane and the second power plane.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Adel Elsherbini, Aleksandar Aleksov, Feras Eid, Henning Braunisch, Thomas L. Sounart, Johanna Swan, Beomseok Choi, Krishna Bharath, William J. Lambert, Kaladhar Radhakrishnan
  • Publication number: 20230096368
    Abstract: An inductor structure, a package substrate, an integrated circuit device, an integrated circuit device assembly and a method of fabricating the inductor structure. The inductor structure includes: an electrically conductive body; and a magnetic structure including a non-electrically-conductive magnetic material, wherein: one of the magnetic structure or the electrically conductive body wraps around another one of the magnetic structure or the electrically conductive body to form the inductor structure therewith; and at least one of the electrically conductive body or the magnetic structure has a granular microstructure including randomly distributed particles presenting substantially non-linear particle-to-particle boundaries with one another.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: Aleksandar Aleksov, Adel Elsherbini, Johanna Swan, Feras Eid, Thomas L. Sounart, Henning Braunisch, Beomseok Choi, Krishna Bharath, Kaladhar Radhakrishnan, William J. Lambert
  • Publication number: 20230097714
    Abstract: In one embodiment, a base die apparatus includes a conformal power delivery structure comprising a first electrically conductive layer defining one or more recesses, and a second electrically conductive layer at least partially within the recesses of the first electrically conductive layer and having a lower surface that generally conforms with the upper surface of the first electrically conductive layer. The conformal power delivery structure also includes a dielectric material between the surfaces of the first electrically conductive layer and the second electrically conductive layer that conform with one another. The conformal power delivery structure may be connected to connection pads of the base die apparatus, e.g., to provide power delivery to integrated circuit (IC) chips connected to the base die apparatus. The base die apparatus also includes bridge circuitry to connect IC chips with one another.
    Type: Application
    Filed: September 24, 2021
    Publication date: March 30, 2023
    Applicant: Intel Corporation
    Inventors: William J. Lambert, Beomseok Choi, Krishna Bharath, Kaladhar Radhakrishnan, Adel Elsherbini
  • Publication number: 20220416393
    Abstract: Waveguide interconnects for semiconductor packages are disclosed. An example semiconductor package includes a first semiconductor die, a second semiconductor die, and a substrate positioned between the first and second dies. The substrate includes a waveguide interconnect to provide a communication channel to carry an electromagnetic signal. The waveguide interconnect is defined by a plurality of through substrate vias (TSVs). The TSVs in a pattern around the at least the portion of the substrate to define a boundary of the communication channel.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Georgios Dogiamis, Johanna Swan, Adel Elsherbini, Shawna Liff, Beomseok Choi, Qiang Yu
  • Publication number: 20220415854
    Abstract: Apparatus and methods are disclosed. In one example, a semiconductor package includes a first die that has a first surface and a first electrical lead at or near the first surface. The semiconductor package also includes a substrate that has a second surface and is coupled to the first die at a first interface. The substrate also includes a first electrode at or near the second surface and at least a first portion of an integrated passive device that is coupled to the first electrode. The first electrode is aligned with and coupled to the first electrical lead across the first interface.
    Type: Application
    Filed: June 25, 2021
    Publication date: December 29, 2022
    Inventors: Georgios Dogiamis, Adel Elsherbini, Qiang Yu, Shawna Liff, Beomseok Choi
  • Publication number: 20220399305
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. In some embodiments, a microelectronic assembly may include a first microelectronic component, embedded in a first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a first magnetic conductive material; and a second microelectronic component, embedded in a second dielectric layer on the first dielectric layer, including a surface and one or more side surfaces at least partially encapsulated by a second magnetic conductive material, wherein the second microelectronic component is coupled to the surface of the first microelectronic component by a hybrid bonding region, and wherein the second magnetic conductive material is coupled to the first magnetic conductive material.
    Type: Application
    Filed: June 9, 2021
    Publication date: December 15, 2022
    Applicant: Intel Corporation
    Inventors: Beomseok Choi, Adel A. Elsherbini, Han Wui Then, Johanna M. Swan, Shawna M. Liff
  • Patent number: 11527489
    Abstract: An apparatus includes a substrate, one or more integrated circuit dies on the substrate, and a stiffener affixed to the substrate. One or more sections of the stiffener may includes a magnetic material. The apparatus further includes an inductive circuit element comprising one or more conductive structures wrapped around the magnetic material. In some examples where a first coil is wrapped around a first section of the stiffener, and a second coil is wrapped around a second section of the stiffener, current supplied to the first coil generates at the second coil a current that is further transmitted to the one or more semiconductor dies.
    Type: Grant
    Filed: June 29, 2018
    Date of Patent: December 13, 2022
    Assignee: Intel Corporation
    Inventors: Michael J. Hill, Mathew Manusharow, Beomseok Choi, Digvijay Raorane
  • Patent number: 11380652
    Abstract: An apparatus is provided which comprises: a first set of one or more contacts on a first die surface, the first set of one or more contacts to couple with contacts of an integrated circuit die, one or more multi-level voltage clamps coupled with the first set of one or more contacts, the one or more multi-level voltage clamps switchable between two or more voltages, one or more integrated voltage regulators coupled with the one or more multi-level voltage clamps, the one or more integrated voltage regulators to provide an output voltage, one or more through silicon vias (TSVs) coupled with the one or more integrated voltage regulators, and a second set of one or more contacts on a second die surface, opposite the first die surface, the second set of one or more contacts coupled with the one or more TSVs, and the second set of one or more contacts to couple with contacts of a package substrate. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: September 29, 2017
    Date of Patent: July 5, 2022
    Assignee: Intel Corporation
    Inventors: Beomseok Choi, Kaladhar Radhakrishnan, William Lambert, Michael Hill, Krishna Bharath
  • Patent number: 11353900
    Abstract: An apparatus is provided, where the apparatus includes a first domain including first one or more circuitries, and a second domain including second one or more circuitries. The apparatus may further include a first voltage regulator (VR) to supply power to the first domain from a power bus, a second VR to supply power to the second domain from the power bus, and a third VR coupled between the first and second domains. The third VR may at least one of: transmit power to at least one of the first or second domains, or receive power from at least one of the first or second domains.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: June 7, 2022
    Assignee: Intel Corporation
    Inventors: Beomseok Choi, Siddharth Kulasekaran, Krishna Bharath