Abstract: A technique is disclosed for providing a charge pump circuit for phase locked loop (PLL) to reduce mismatch of up/down currents and feed-through of up/down currents to voltage output. Elimination of feed-through of the input signal may be achieved by using differential switches (M1 and M2, and M3 and M4) based on DC reference voltage in the charge pump and also eliminate the mismatch of up/down currents in a wide voltage output range by applying a new replica biasing using feedback.

Abstract: A system and method are disclosed for providing a DLL with false lock protector to avoid false lock and ensure accurate lock. The false lock protector operates when the initial delay time between signals from an input reference clock and an output clock exceeds the lock range during operation of the DLL. The DLL with false lock protector includes a reference clock, a delay line composed of several delay cells connected in series, a phase detector, comparator for comparing phases of signals from the reference and output clocks, a determinator and a controller for controlling the delay of the delay line.

Abstract: An apparatus for recovering symbol timing in a CAP-based high-speed communication system such as an ADSL or VDSL, using a single-sided prefilter pair, in which timing information is obtained by means of the single-sided prefilter pair and a multiplier instead of a squaring unit used in general communication systems, for the recovery of accurate data, so that the symbol timing can be recovered through a digital signal process at a clock rate which is four times as high as a symbol transmission rate. According to the present invention, the single-sided prefilter pair and multiplier are used instead of the squaring unit spreading a frequency band. Therefore, the frequency band is not spread, so that the timing can be obtained with no signal overlapping due to sampling, although a sampling frequency is four times as high as a symbol frequency.

Abstract: A cascaded voltage controlled oscillator is described that includes a first oscillator stage having a first oscillator stage first input, a first oscillator stage second input and a first oscillator stage output. A second oscillator stage includes a second oscillator stage input and a second oscillator stage output wherein the first oscillator stage output is input to the second oscillator stage input and wherein the second oscillator stage output is fed back to the first oscillator stage second input. A third oscillator stage includes a third oscillator stage input and a third oscillator stage output wherein the second oscillator stage output is fed to the third oscillator stage input.

Abstract: A new linearized transconductance circuit for converting an input into an output has been achieved. This linearized transconductance circuit is especially suited for application in a mixing circuit using a double-balanced cell. The circuit allows optimization of linearity and noise figure without excessive current. The input comprises first and second phases having a differential voltage therebetween. The output comprises first and second phases having a differential current therebetween that is proportional to the differential voltage. The circuit comprises, firstly, first, second, third, and fourth MOS transistors, with each transistor having a gate, a drain, and a source. The gates of the first and third MOS transistors are coupled to the input first phase. The drains of the first and third transistors are coupled to the output first phase. The gates of the second and fourth MOS transistors are coupled to the input second phase.

Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop

Abstract: The present invention relates to a sigma-delta analog-to-digital converter using a mixed mode integrator composed of an analog integrator and a digital integrator, which can prevent the performance degradation due to the saturation of an integrator of the overload of a quantizer. A sigma-delta analog-to-digital converter having an anti-aliasing filter, a sample and hold circuit, a sigma-delta modulator and a decimation filter comprises an overload estimating unit for judging the saturation or overload of an analog integrator; a mixed mode integrator which has the analog integrator and a digital integrator composed of a digital adder and a digital storing unit and integrates the output of the overload estimating unit in analog or digitally; and a quantization unit for converting the output of the mixed mode integrator to a digital signal.

Abstract: The present invention relates to a ring oscillator VCO using a differential delay stage, substantially increasing the oscillation frequency. The differential delay stage utilizes a differential latch together with a pair of PMOS transistors taking the input signals through skewed delay paths. The added control NMOS transistors controls the strength of said latch and makes the ring oscillator variable in oscillation frequency.

Abstract: Disclosed is a self-calibration device for calibrating a phase difference between output waveforms of a ring oscillator, comprising: a voltage-controlled oscillator adapted to adjust the transition time of an output signal according to an inputting of a control voltage for controlling the phase offset and generate the adjusted output signal; a divider adapted to divide a frequency of the output signal generated from the voltage-controlled oscillator by a fractional number to generate a plurality of output waveforms having different phases with them having an identical phase difference each other; a phase-locked loop (PLL) circuit adapted to correctly make a frequency and phase of the output signal of the divider coincident with those of a system clock, the phase-locked loop (PLL) circuit including at least a phase-frequency detecting means adapted to compare the frequency and phase of the output signal with those of the system clock and to output a result of the comparison; and a phase offset calibrating loop

Abstract: A low-power sense amplifier for a memory is provided, which includes a differential amplifier for sensing and amplifying a weak voltage signal of a bit line connected to a memory cell, and a latch amplifier for storing data inputted thereto, the latch amplifier being operated by the output signal of the differential amplifier, the sense amplifier including a bias means constructed of transistors which are included in the differential amplifier and turned on or turned off by a control signal, the transistors providing a load resistor component required for driving the differential amplifier when it is turned on, and a cutoff means for turning off the transistors constructing the bias means to stop the operation of the differential amplifier when there is a first logic state signal among the output signals of the latch amplifier. Accordingly, the low-power sense amplifier for a memory can perform high-speed sense amplification of bit line signal and prevent unnecessary power consumption.

Abstract: A data communication receiver includes conventional means for receiving and demodulating a synchronous pulse amplitude modulated signal to provide baseband I and Q signals. A pair of absolute value generators process the baseband I and Q signals to provide absolute value I and Q signals which are combined to form a combined I and Q signal. The combined I and Q signal is applied to a third absolute value generator, the output of which is filtered by a baud rate or higher rate with a low order filter to produce a recovered clock signal.