Abstract: A transistor with a shared gate structure includes an active area and a gate. The active area has a body extending in a first direction on a substrate, and a protrusion extending in a second direction perpendicular to the first direction from a central portion of the body in the first direction. The gate is arranged above the active area to overlap a channel area of the active area, and has an inverted pi () structure that, from a plan view, surrounds on three sides but does not cover a portion of the active area that includes two corner portions of the active area. The active area is divided into a first active area and a second active area by a separation area extending in the second direction and separating the body and a portion of the protrusion. The protrusion is divided into a first portion separated into two sub-portions by the separation area and a second portion, wherein the first portion is between the body and the second portion in the second direction.

Abstract: A semiconductor device includes a buried insulation layer pattern on a lower substrate. A first semiconductor pattern and a second semiconductor pattern pattern are disposed on on the buried insulation layer pattern. A lower conductive pattern is formed in a lower portion of a first recess between the first and second semiconductor patterns, and the lower conductive pattern may contact lower sidewalls of the first and second semiconductor patterns. A common gate structure formed on the lower conductive pattern fills a remaining portion of the first recess. The first semiconductor pattern may include a first impurity region, a first channel region, and a second impurity region sequentially stacked from an upper surface of the first semiconductor towards the lower substrate. The second semiconductor pattern includes a third impurity region, a second channel region, and a fourth impurity region.

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

Abstract: A transistor with a shared gate structure includes an active area and a gate. The active area has a body extending in a first direction on a substrate, and a protrusion extending in a second direction perpendicular to the first direction from a central portion of the body in the first direction. The gate is arranged above the active area to overlap a channel area of the active area, and has an inverted pi () structure that, from a plan view, surrounds on three sides but does not cover a portion of the active area that includes two corner portions of the active area. The active area is divided into a first active area and a second active area by a separation area extending in the second direction and separating the body and a portion of the protrusion. The protrusion is divided into a first portion separated into two sub-portions by the separation area and a second portion, wherein the first portion is between the body and the second portion in the second direction.

Abstract: A semiconductor device includes a substrate, a peripheral circuit layer, a first active pattern, a gate electrode, a first insulating layer, a conductive contact, and a second active pattern. The peripheral circuit layer is disposed on the substrate, and the peripheral circuit layer includes logic transistors and an interconnection layer that is disposed on the logic transistors. The first active pattern is disposed on the peripheral circuit layer. The gate electrode is disposed on a channel region of the first active pattern. The first insulating layer is disposed on the first active pattern and the gate electrode. The conductive contact is disposed in the first insulating layer and is electrically connected to a first source/drain region of the first active pattern, and the second active pattern is disposed on the first insulating layer. The channel region of the second active pattern vertically overlaps with the conductive contact.

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

Abstract: A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

Abstract: A ferroelectric semiconductor device includes an active region extending in one direction, a gate insulating layer crossing the active region, a ferroelectric layer disposed on the gate insulating layer and including a hafnium oxide, a gate electrode layer disposed on the ferroelectric layer, and source/drain regions disposed on the active region to be adjacent to both sides of the gate insulating layer, wherein the ferroelectric layer includes 20% or more of orthorhombic crystals, and an upper surface of the source/drain region is located at a level equal to or higher than an upper surface of the ferroelectric layer.

Abstract: A semiconductor memory device includes a substrate, a first active pattern on the substrate, a gate electrode intersecting a channel region of the first active pattern, a first insulating layer covering the first active pattern and the gate electrode, a contact penetrating the first insulating layer so as to be electrically connected to a first source/drain region of the first active pattern, and a second active pattern on the first insulating layer. A channel region of the second active pattern vertically overlaps with the contact.