Patents by Inventor Bernadette Ann Pierson
Bernadette Ann Pierson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7996346Abstract: A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.Type: GrantFiled: December 19, 2007Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Robert H. Bell, Jr., Louis Bennie Capps, Jr., Thomas Edward Cook, Thomas J. Dewkett, Naresh Nayar, Ronald Edward Newhart, Bernadette Ann Pierson, Michael Jay Shapiro
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Patent number: 7630915Abstract: An intellectual property management facility for proactively creating, developing and managing an intellectual property portfolio includes: determining available resource capacity for an intellectual property activity in a tracking system; assigning technical attributes to the activity in the tracking system; apportioning resource capacity for the activity by technical attribute based on the value assigned to each of the technical attributes and based on available resource capacity; obtaining actual resource usage by technical attribute from the tracking system; and managing resource allocation for the intellectual property activity by determining the difference between the actual resource usage and the resource allocation by technical attribute.Type: GrantFiled: June 14, 2006Date of Patent: December 8, 2009Assignee: International Business Machines CorporationInventors: John Anthony Bracchitta, Patricia McGuiness Marmillion, Bernadette Ann Pierson, Henry Charles Rickers, Howard J. Walter, Jr.
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Publication number: 20090164399Abstract: A multiprocessor system which includes automatic workload distribution. As threads execute in the multiprocessor system, an operating system or hypervisor continuously learns the execution characteristics of the threads and saves the information in thread-specific control blocks. The execution characteristics are used to generate thread performance data. As the thread executes, the operating system continuously uses the performance data to steer the thread to a core that will execute the workload most efficiently.Type: ApplicationFiled: December 19, 2007Publication date: June 25, 2009Inventors: Robert H. Bell, JR., Louis Bennie Capps, JR., Thomas Edward Cook, Thomas J. Dewkett, Naresh Nayar, Ronald Edward Newhart, Bernadette Ann Pierson, Michael Jay Shapiro
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Patent number: 7089192Abstract: An intellectual property management facility for proactively creating, developing and managing an intellectual property portfolio includes: determining available resource capacity for an intellectual property activity in a tracking system; assigning technical attributes to the activity in the tracking system; apportioning resource capacity for the activity by technical attribute based on the value assigned to each of the technical attributes and based on available resource capacity; obtaining actual resource usage by technical attribute from the tracking system; and managing resource allocation for the intellectual property activity by determining the difference between the actual resource usage and the resource allocation by technical attribute.Type: GrantFiled: December 22, 2000Date of Patent: August 8, 2006Assignee: International Business Machines CorporationInventors: John Anthony Bracchitta, Patricia McGuinness Marmillion, Bernadette Ann Pierson, Henry Charles Rickers, Howard J. Walter, Jr.
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Patent number: 6242778Abstract: In a silicon on insulator technology, cooling channels in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer, where the junction regions are separated from the substrate by an insulating layer. In a second embodiment, thermal conductors in a support substrate are located substantially under the junction regions of selected individual active devices in a semiconductor layer where the junction regions are separated from the substrate by an insulating layer. Optionally, either the cooling channels or the thermal conductors may be enlarged such that a plurality of devices may be cooled by a single cooling channel or thermal conductor.Type: GrantFiled: September 22, 1998Date of Patent: June 5, 2001Assignee: International Business Machines CorporationInventors: Patricia McGuinness Marmillion, Anthony Michael Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt
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Patent number: 5925924Abstract: Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.Type: GrantFiled: April 14, 1997Date of Patent: July 20, 1999Assignee: International Business Machines CorporationInventors: John Edward Cronin, Wayne John Howell, Howard Leo Kalter, Patricia Ellen Marmillion, Anthony Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt
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Patent number: 5691248Abstract: Integrated Circuit ("IC") chips are formed with precisely defined edges and sizing. At the wafer processing level, trenches are lithographically etched in the kerf regions to define the edges of the IC chips on the wafer. The trenches are filled with insulating material, and upper level wiring and metallization is completed for the IC chips on the wafer. Further trenches are defined down to the filled previously formed trenches. The wafer is thinned from its bottom up to the filled trenches, and the insulating material therein is removed to separate the individual IC chips from the wafer. The precision of IC chip edge definition facilitates forming the IC chips into stacks more easily because many stack level alignment processes become unnecessary.Type: GrantFiled: July 26, 1995Date of Patent: November 25, 1997Assignee: International Business Machines CorporationInventors: John Edward Cronin, Wayne John Howell, Howard Leo Kalter, Patricia Ellen Marmillion, Anthony Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt
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Patent number: 5679609Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.Type: GrantFiled: April 12, 1996Date of Patent: October 21, 1997Assignee: International Business Machines CorporationInventors: Bruno Roberto Aimi, John Edward Cronin, Andre Conrad Forcier, James Marc Leas, Patricia McGuinnes Marmillion, Anthony Michael Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt
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Patent number: 5661330Abstract: A multichip semiconductor structure and fabrication method having connect assemblies with fuses which facilitate burn-in stressing and electrical testing of the structure are presented. The structure comprises a multichip stack having standard transfer wire outs to an edge surface thereof. At least some wire outs to the edge surface have fuses electrically series connected thereto such that should an excessive current source/sink arise during burn-in stressing, the corresponding fuse will open circuit. A conductive structure is also disclosed that facilitates the formation of final, operational metallization wiring on the edge surface of the multichip structure prior to burn-in stressing and testing. This conductive structure includes a first conductive level and a second conductive level. The first conductive level has isolated conductors with ends disposed in close proximity.Type: GrantFiled: March 14, 1995Date of Patent: August 26, 1997Assignee: International Business Machines CorporationInventors: Bruno Roberto Aimi, John Edward Cronin, Andre Conrad Forcier, James Marc Leas, Patricia McGuinnes Marmillion, Anthony Michael Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt
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Patent number: 5651857Abstract: Improved film spacers for the sidewalls within semiconductor structures are disclosed. The spacers are made of non-conformal, organic materials, such as polyimides, acrylates, methacrylates, and various photoresist compositions. They are formed on the sidewalls by a process which involves the formation of overhang structures. The film spacers may be used for a variety of applications, such as sidewall imaging, control of dopant diffusion in an FET, formation of borderless contacts, and the manufacture of a resistor from an FET.Type: GrantFiled: September 8, 1995Date of Patent: July 29, 1997Assignee: International Business Machines CorporationInventors: John Edward Cronin, Patricia Ellen Marmillion, Anthony Palagonia, Bernadette Ann Pierson, Dennis Arthur Schmidt