Abstract: An integrated circuit chip for controlling the transmission of data between a host peripheral device and other peripheral devices or a remote processor in which the transmission of data takes place in either a processor interrupt mode or a direct memory access mode. The integrated circuit chip includes first, second, third and fourth sequentially located edges forming a rectangle. The chip further includes input circuitry located generally adjacent the corner formed by the third and fourth edges and output circuitry located adjacent the first edge. A plurality of counters/registers associated with the input and output circuits are located adjacent the third edge. A Command register located adjacent the third edge selects the transfer mode and controls the operation of the integrated circuit chip in either an output or input mode. The chip may operate in a transmit only mode, receive only mode or transmit and receive modes simultaneously.

Abstract: An integrated circuit for operatively connecting a plurality of peripheral devices to a processor includes first, second, third and fourth sequentially located edges forming a rectangle. The integrated circuit includes two independent full duplex, master peripheral ports in which each port provides two character buffering on both input and output channels. Data may be transmitted using two message formats at two different clock frequencies with each channel having simultaneous sending and receiving capabilities. Data processing circuits are located adjacent the first edge which connects to the processor while the port control circuitry is located adjacent the third edge of the chip which connects to the peripheral devices.