Abstract: An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits for the clock in the domino pipeline, ensuring that a domino data never goes to precharge, and therefore is lost before it is consumed, ensuring that the domino datapath operates at any speed below the maximum operating speed, ensuring that domino signals leaving the design through primary outputs of a static block are latched to prevent the precharge to overwrite the evaluated results, providing an optimal solution in terms of performance, area and power, defining some constraints that are checked and enforced by the downstream tools in order to guaranty the proper functionality of the design.

Abstract: A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthesized and a set of timing and physical constraints. The unate step includes reading the design and initializing, simplifying the logic, marking inversions, marking binate cones for duplication, identifying endpoints, performing a reverse traversal, an optional phase optimization, committing netlist changes, primary inputs processing, primary outputs processing, and a final check and save.

Abstract: A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design.

Abstract: A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the clock network and clock tree synthesis. A domino logic circuit including at least one logic gate including a fast input and a slow input, and a static buffer inserted in series with the fast input of the logic gate. The falling time of the static buffer is set to be greater than a defined minimum falling time and less than a defined maximum falling time.

Abstract: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase duty cycle relative to the second clock signal. The positive phase of the first clock signal is shortened by an amount greater than or equal to a precharge time plus a falling edge skew between the clock signals. The footer transistor in the second domino gate can be eliminated. The first and second clock signals have the same frequency. The timing of the data presented to the first domino gate, and the first and second clock signals is adjusted so that there is no direct path between the power supply voltage and ground during the entire precharge phase of the second domino gate.

Abstract: A domino clocking method includes providing a domino logic circuit including first and second coupled domino gates, providing a first clock signal for clocking the first domino gate, and providing a second clock signal for clocking the second domino gate, wherein the first clock signal has a shortened positive phase duty cycle relative to the second clock signal. The positive phase of the first clock signal is shortened by an amount greater than or equal to a precharge time plus a falling edge skew between the clock signals. The footer transistor in the second domino gate can be eliminated. The first and second clock signals have the same frequency. The timing of the data presented to the first domino gate, and the first and second clock signals is adjusted so that there is no direct path between the power supply voltage and ground during the entire precharge phase of the second domino gate.

Abstract: An automatic method for assigning the clock phases on a domino datapath embedding static gates includes replacing domino cells on non-critical paths by a static equivalent cell, delaying the clock arrival on domino gates driven by static signals, ensuring that critical data never waits for the clock in the domino pipeline, ensuring that a domino data never goes to precharge, and therefore is lost before it is consumed, ensuring that the domino datapath operates at any speed below the maximum operating speed, ensuring that domino signals leaving the design through primary outputs of a static block are latched to prevent the precharge to overwrite the evaluated results, providing an optimal solution in terms of performance, area and power, defining some constraints that are checked and enforced by the downstream tools in order to guaranty the proper functionality of the design.

Abstract: A primarily domino logic block uses static buffers instead of clocked domino buffers to correct a phase skipping problem, while realizing the same logic function with less integrated circuit area, power consumption, and cost. The use of static buffers simplifies the clock network and clock tree synthesis. A domino logic circuit including at least one logic gate including a fast input and a slow input, and a static buffer inserted in series with the fast input of the logic gate. The falling time of the static buffer is set to be greater than a defined minimum falling time and less than a defined maximum falling time.

Abstract: A fully automated ASIC style domino synthesis flow is provided for mapping a digital logic design onto a domino logic library. The input to the flow is the same as for standard static synthesis environments and includes an RTL description of the design to be synthesized and a set of timing and physical constraints. The unate step includes reading the design and initializing, simplifying the logic, marking inversions, marking binate cones for duplication, identifying endpoints, performing a reverse traversal, an optional phase optimization, committing netlist changes, primary inputs processing, primary outputs processing, and a final check and save.

Abstract: A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design.

Abstract: A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).

Abstract: A method for synthesizing a domino logic circuit design (18) from a source circuit definition (14) using a static logic circuit synthesis tool (12) includes generating a preliminary domino logic circuit (26) design using the circuit synthesis tool (12) and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design (30).