Patents by Inventor Bernard C. Dewitt

Bernard C. Dewitt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Data processing system having scan testing using set latches for selectively observing test data
    Patent number: 5210759
    Abstract: A data processing system uses a scannable test circuit to provide transistor fault testing of a large amount of random transistor logic. In a test mode of operation, a plurality of Master-Slave latches are used to observe the output of a plurality of data path drivers activated during a scan test operation. The data path drivers are included as part of the random transistor logic, and the outputs of the data path drivers are connected to a set input of the Master portion of one of a plurality of Master-Slave latches. The Master-Slave latches can be scanned to provide a test signal providing transistor fault information in the data processing system.
    Type: Grant
    Filed: November 19, 1990
    Date of Patent: May 11, 1993
    Assignee: Motorola, Inc.
    Inventors: Bernard C. DeWitt, Michael G. Gallup
  • Sticky bit detection and shifting logic
    Patent number: 4999796
    Abstract: A circuit which concurrently performs bit shifting for floating point arithmetic and sticky bit determination. An input data operand is presented to the circuit along with a control signal which determines the number of digit positions to be shifted. While shifting of bits occurs to provide a shifted output operand, detection of bits which are shifted off from the output operand for the presence of sticky bits occurs. A shifted output operand and a sticky bit detect signal are provided substantially concurrently. An efficient layout of the circuit significantly minimizes the area required to implement both functions.
    Type: Grant
    Filed: December 14, 1989
    Date of Patent: March 12, 1991
    Assignee: Motorola, Inc.
    Inventors: Bernard C. DeWitt, Ying-wai Ho
  • Inverting latching bootstrap driver with V.sub.dd *2 booting
    Patent number: 4902919
    Abstract: An inverting latching bootstrap driver is used to drive a load where the input to the driver may change during the driving phase. The input to the driver circuit is controlled by a precharge/discharge type decoder. The bootstrap driver samples the input during the same phase the decoder discharges, and isolates the input while the decoder precharges. Accordingly, the decoder is precharged during the same phase that the bootstrap output is driven. The circuit implementation uses a transistor in series with the enhancement device of the inverter to disable the inverter while the bootstrap is fired. Since the device used to isolate the booting charge is a depletion mode device, the booting node will be able to rise to a full V.sub.DD *2.
    Type: Grant
    Filed: September 26, 1988
    Date of Patent: February 20, 1990
    Assignee: Motorola, Inc.
    Inventors: Thomas S. Spohrer, Bernard C. Dewitt