Patents by Inventor Bernard Charles

Bernard Charles has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070013709
    Abstract: The invention proposes a process for rendering an object view using a PLM database. The database comprises modeled objects and relations between said modeled objects. Said modeled objects are associated to a set of values of attributes, whose values are stored in the database or computable based on relations involving said modeled objects. The process comprises displaying to the user a view of a set of modeled objects; receiving a selection by a user of an attribute; querying the database for a modeled object to be rendered; providing a value of the selected attribute, associated to said modeled object; and rendering said modeled object in the view according to the provided value of the attribute. It is also possible for the user to select a value of an attribute and the rendering will be carried out only on the object, whose value(s) matches with the selected value.
    Type: Application
    Filed: December 19, 2005
    Publication date: January 18, 2007
    Inventors: Bernard Charles, Arnaud Nonclercq, Guenole Gicquel, Francois Perroux, Duy Vu
  • Patent number: 7136954
    Abstract: A communications bus for a digital device includes a credit-based flow control mechanism, in which a sending component maintains a local record of its credits. Credits are returned to the sender by pulsing a single-bit credit return line. A separate mechanism provides a count of available credits from the receiver, the separate mechanism not necessarily being current. The local record is compared to the count of credits from the separate mechanism over a pre-determined time interval, failure of the two values to agree at any time during the interval indicating a probable credit discrepancy. A credit discrepancy is confirmed, preferably by suspending certain bus activity for a sufficiently long period to account for any delay in propagating credit value changes, and re-comparing the values. Preferably, the bus communicates between internal components of an integrated circuit chip.
    Type: Grant
    Filed: January 31, 2005
    Date of Patent: November 14, 2006
    Assignee: International Business Machines Corporation
    Inventors: Mark Anthony Check, Bernard Charles Drerup, Michael Grassi
  • Patent number: 7127562
    Abstract: A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.
    Type: Grant
    Filed: June 11, 2003
    Date of Patent: October 24, 2006
    Assignee: International Business Machines Corporation
    Inventors: James Norris Dieffenderfer, Bernard Charles Drerup, Jaya Prakash Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Barry Joe Wolford
  • Publication number: 20060212821
    Abstract: The invention is directed to a product edition and simulation system, comprising a storage system having data related to modeled object. The product edition and simulation system has a graphical user interface, having an edition workbench comprising a plurality of software tools suitable for editing a subset of features of the modeled objects. The edition workbench is adapted for displaying a user-interactive graphical tool in the graphical user interface. The graphical tool is adapted for triggering, upon user action, a simulation of a modeled object according to a feature not comprised in the subset, the simulation using a result of a query in the storage system.
    Type: Application
    Filed: December 19, 2005
    Publication date: September 21, 2006
    Inventors: Bernard Charles, Arnaud Nonclercq, Francois Perroux
  • Patent number: 7074429
    Abstract: Stable tablets comprising fosinopril sodium are prepared by employing either stearic acid or zinc stearate as the lubricant.
    Type: Grant
    Filed: January 11, 2002
    Date of Patent: July 11, 2006
    Inventor: Bernard Charles Sherman
  • Publication number: 20060136842
    Abstract: The invention proposes interacting with a database having data related to modeled products and parts using a graphical user interface displayed by a computer. The graphical user interface is adapted to allow a user to access the database. The method also includes providing within the graphical user interface a toolbar with at least one field suitable for displaying an argument. The toolbar is adapted for allowing a user to execute a function using the argument. The method further includes the steps of querying the database and updating the argument displayed in the field using a result of the querying step.
    Type: Application
    Filed: August 10, 2005
    Publication date: June 22, 2006
    Inventors: Bernard Charles, Guenole Gicquel, Francois Perroux, Duy-Minh Vu
  • Patent number: 7035958
    Abstract: A method of operating a request FIFO of a system on a chip (SoC) in which a requests in a first position that has been granted and which subsequently receives a retry from the intended target is automatically re-ordered with respect to the other requests below it in the request FIFO. Each issued requests is tagged to either enable or disable a re-order feature. When a request that is tagged as re-order enabled is granted, the FIFO logic monitors the response provided for the request. If the response is a retry, the request is removed from the first position of the request FIFO and the next sequential request is moved into the first position. The removed requests may be re-ordered within the request FIFO or sent back to the initiator. In the former implementation, controller logic reorders the first request within the request FIFO.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: April 25, 2006
    Assignee: International Business Machines Corporation
    Inventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard Charles Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford
  • Patent number: 7003064
    Abstract: In one form, apparatus for aligning clock signals includes first and second logic circuitry for receiving respective first and second clock signals. The first and second clock signals are substantially synchronized and operations of the first logic circuitry and second logic circuitry are clocked by the respective first and second clock signals. The first logic circuitry receives a third clock signal derived from the second clock signal, and by repeatedly sampling the third clock signal with the first clock signal, the first logic circuitry repeatedly detects relative phase relations of the first and third clock signals. The second logic circuitry adjusts the phase of the third clock signal responsive to an accumulation of the phase relation detecting.
    Type: Grant
    Filed: January 7, 2002
    Date of Patent: February 21, 2006
    Assignee: International Business Machines Corporation
    Inventors: Bernard Charles Drerup, Richard Siegmund, Jr.
  • Patent number: 6985972
    Abstract: A data processing system with a snooper that is capable of dynamically enabling and disabling its snooping capabilities (i.e., snoop detect and response). The snooper is connected to a bus controller via a plurality of interconnects, including a snooperPresent signal, a snoop response signal and a snoop detect signal. When the snooperPresent signal is asserted, subsequent snoop requests are sent to the snooper, and the snooper is polled for a snoop response. Each snooper is capable of responding at different times (i.e., each snooper operates with different snoop latencies). The bus controller individually tracks the snoop response received from each snooper with the snooperPresent signal enabled. Whenever the snooper wishes to deactivate its snooping capabilities/operations, the snooper de-asserts the snooperPresent signal. The bus controller recognizes this as an indication that the snooper is unavailable.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: January 10, 2006
    Assignee: International Business Machines Corporation
    Inventors: James Norris Dieffenderfer, Bernard Charles Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Barry Joe Wolford
  • Patent number: 6973520
    Abstract: An electronic system is disclosed, including multiple initiators and one or more targets coupled to a bus, and a request mask control unit (RMCU). The initiators are configured to initiate requests (e.g., read requests and write requests) via the bus, and the targets are configured to receive requests from the initiators via the bus. The targets are also configured to produce multiple MaskEnable signals, wherein each of the MaskEnable signals is generated following an initial request received via the bus, and dependent on a corresponding “masking situation” within the target. The RMCU receives the MaskEnable signals and produces multiple RequestMask signals dependent upon the MaskEnable signals. One or more of the initiators are permitted to repeat requests via the bus dependent upon one or more of the RequestMask signals. This mechanism provides additional bus bandwidth for carrying out successful data transfers.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: December 6, 2005
    Assignee: International Business Machines Corporation
    Inventors: Bernard Charles Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Richard Nicholas Iachetta, Jr., Barry Joe Wolford
  • Patent number: 6914141
    Abstract: Pharmaceutical tablets comprising clopidogrel bisulfate and a lubricant selected from zinc stearate, stearic acid, and sodium stearyl fumarate.
    Type: Grant
    Filed: November 4, 2002
    Date of Patent: July 5, 2005
    Inventor: Bernard Charles Sherman
  • Patent number: 6907502
    Abstract: A method for prioritizing snoop pushes in a data processing system that schedules requests within a request FIFO. Each new request that is received is placed in the last position of the request FIFO and the request FIFO typically grants request based solely on the order within the request FIFO. As prior requests are sequentially granted the subsequent requests move closer to a first position of the request FIFO. However, when a snoop push is received at the request FIFO, the snoop push is automatically inserted at the first position of the request FIFO ahead of all yet to be granted requests within the request FIFO.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: June 14, 2005
    Assignee: International Business Machines Corporation
    Inventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard Charles Drerup, Jaya Prakash Subramaniam Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Barry Joe Wolford
  • Patent number: 6894066
    Abstract: A process of producing the magnesium salt of an enantiomer of omeprazole, said process comprising the steps of: i) reacting magnesium with a lower alcohol to produce magnesium alkoxide in solution in the lower alcohol as solvent, ii) adding the neutral form of the enantiomer of omeprazole to the solution, and iii) flash-evaporating the solvent.
    Type: Grant
    Filed: May 16, 2003
    Date of Patent: May 17, 2005
    Inventor: Bernard Charles Sherman
  • Patent number: 6834378
    Abstract: A method of designing a system on a chip (SoC) to operate with varying latencies and frequencies. A layout of the chip is designed with specific placement of devices, including a bus controller, initiator, and target devices. The time for a signal to propagate from a source device to a destination device is determined relative to a default propagation time. A pipeline stage is then inserted into a bus path between said source device and destination device for each additional time the signal takes to propagate. Each device (i.e., initiators, targets, and bus controller) is designed with logic to control a protocol that functions with a variety of response latencies. With the additional logic, the devices do not need to be changed when pipeline stages are inserted in the various paths. Registers are utilized as the pipeline stages that are inserted within the paths.
    Type: Grant
    Filed: October 3, 2002
    Date of Patent: December 21, 2004
    Assignee: International Business Machines Corporation
    Inventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard Charles Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford
  • Publication number: 20040255085
    Abstract: A method and system for ensuring orderly forward progress in granting snoop castout requests. Masters may include a tag (“request tag”) in their transfer requests to a bus macro. The request tag indicates the order of the request issued by the master. If the bus macro determines that the transfer request is snoopable, then the bus macro broadcasts a snoop request that includes the request tag. If a snoop controller determines that the address in the snoop request is a hit to a modified coherency granule in an associated cache, then the master associated with that snoop controller transmits a castout request to the bus macro that includes the request tag associated with the snoop request. The bus macro uses the request tag to determine whether the castout request is a response to the oldest in a series of pipelined snoop requests to be serviced.
    Type: Application
    Filed: June 11, 2003
    Publication date: December 16, 2004
    Applicant: International Business Machines Corporation
    Inventors: James Norris Dieffenderfer, Bernard Charles Drerup, Jaya Prakash Ganasan, Richard Gerard Hofmann, Thomas Andrew Sartorius, Thomas Philip Speier, Barry Joe Wolford
  • Patent number: 6826656
    Abstract: A method and system for reducing power in a snooping cache based environment. A memory may be coupled to a plurality of processing units via a bus. Each processing unit may comprise a cache controller coupled to a cache associated with the processing unit. The cache controller may comprise a segment register comprising N bits where each bit in the segment register may be associated with a segment of memory divided into N segments. The cache controller may be configured to snoop a requested address on the bus. Upon determining which bit in the segment register is associated with the snooped requested address, the segment register may determine if the bit associated with the snooped requested address is set. If the bit is not set, then a cache search may not be performed thereby mitigating the power consumption associated with a snooped request cache search.
    Type: Grant
    Filed: January 28, 2002
    Date of Patent: November 30, 2004
    Assignee: International Business Machines Corporation
    Inventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard Charles Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford
  • Patent number: 6819726
    Abstract: The invention includes a circuit for aligning the phase of a clock derived from a frequency multiplied version of a reference clock used in a computer system. The dynamic phase alignment circuit includes a few logic gates to perform the operation of delaying the derived clock, detecting its phase misalignment, and correcting such misalignment by incrementally aligning the phase of the derived clock to the reference clock. The invention is capable of aligning the phase of a derived clock to a reference clock in a computer system whose CPU operates at as high a frequency as about 500 MHz or higher.
    Type: Grant
    Filed: December 7, 2000
    Date of Patent: November 16, 2004
    Assignee: International Business Machines Corporation
    Inventors: Bernard Charles Drerup, Richard Siegmund, Jr.
  • Publication number: 20040221086
    Abstract: A first device is operable to communicate on an bus according to a first protocol. A bridge is also operable to communicate on the bus according to the first protocol. A second device is coupled to the bus via the bridge and operable to communicate according to a second protocol. The bridge has a memory for holding data received from the second device and is operable to translate from the second to the first protocol. The second device sends write data responsive to receiving a ready signal from the bridge, and includes memory for holding the write data that the second device has sent, but for which completion has not been signaled. The second device re-sends the write data from the memory responsive to receiving a non-completion signal via the bridge, and releases the memory for the data responsive to receiving a completion signal via the bridge.
    Type: Application
    Filed: April 17, 2003
    Publication date: November 4, 2004
    Applicant: International Business Machines Corporation
    Inventors: Bernard Charles Drerup, Harm Peter Hofstee, Wendel Glenn Voigt, Barry Joe Wolford
  • Publication number: 20040208980
    Abstract: The present invention is directed to an ambient stable and starch-comprising food product. The food product has a base component with at least 8.0% by weight carbohydrate, at least 0.2% by weight amylose and no more than 12.5% by weight amylose. The food product is ambient stable and is not sour, even at a pH below 4.25.
    Type: Application
    Filed: April 16, 2003
    Publication date: October 21, 2004
    Applicant: Unilever Bestfoods North America
    Inventors: Thomas Vincent Merolla, Bernard Charles Sekula
  • Patent number: 6807608
    Abstract: A method and system for performing variable-sized memory coherency transactions. A bus interface unit coupled between a slave and a master may be configured to receive a request (master request) comprising a plurality of coherency granules from the master. Each snooping unit in the system may be configured to snoop a different number of coherency granules in the master request at a time. Once the bus interface unit has received a collection of sets of indications from each snooping logic unit indicating that the associated collection of coherency granules in the master request have been snooped by each snooping unit and that the data at the addresses for the collection of coherency granules snooped has not been updated, the bus interface unit may allow the data at the addresses of those coherency granules not updated to be transferred between the requesting master and the slave.
    Type: Grant
    Filed: February 15, 2002
    Date of Patent: October 19, 2004
    Assignee: International Business Machines Corporation
    Inventors: Victor Roberts Augsburg, James Norris Dieffenderfer, Bernard Charles Drerup, Richard Gerard Hofmann, Thomas Andrew Sartorius, Barry Joe Wolford