Abstract: A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

Abstract: A processor is described that includes a plurality of compute units. One or more test pattern generators generates one or more test patterns and inputs the one or more test patterns into one or more of the plurality of compute units during testing, which testing includes processing of the one or more test patterns by one or more of the plurality of compute units. One or more control and sequencing logic units identifies an idle period during normal use of the processor in which a compute unit of the plurality of compute units is idle. The one or more control and sequencing units controls the test pattern generator to generate and input the one or more test patterns to the idle compute unit and controls the compute unit to process the one or more test patterns during the idle period. One or more comparators compares a result of testing with an expected result of testing to determine if the compute unit is functioning correctly.

Abstract: A method, apparatus, and system for timing synchronization between multiple computing nodes in an autonomous vehicle host system is disclosed. Timing of a first computing node of an autonomous vehicle host system is calibrated based on an external time source. A first timing message is transmitted from the first computing node to a second computing node of the autonomous vehicle host system via a first communication channel between the first computing node and the second computing node. Timing of the second computing node is calibrated based on the first timing message, wherein immediately subsequent to the calibration of timing of the second computing node, timing of the first computing node and of the second computing node is synchronized.

Abstract: A method, apparatus, and system for timing synchronization between multiple computing nodes in an autonomous vehicle host system is disclosed. Timing of a first computing node of an autonomous vehicle host system is calibrated based on an external time source. A first timing message is transmitted from the first computing node to a second computing node of the autonomous vehicle host system via a first communication channel between the first computing node and the second computing node. Timing of the second computing node is calibrated based on the first timing message, wherein immediately subsequent to the calibration of timing of the second computing node, timing of the first computing node and of the second computing node is synchronized.

Abstract: A wireless device having processor circuitry; and a hardware circuit configured to implement, during an active steady-state of a Medium Access Control/Link Layer (MAC/LL) with scheduled channel access, a MAC/LL function without processor circuitry intervention, wherein the steady-state is a state that is control packet transmission free for managed connections in connection oriented communications or a continuous broadcast or scan operation in connectionless communications.

Abstract: A wireless device having processor circuitry; and a hardware circuit configured to implement, during an active steady-state of a Medium Access Control/Link Layer (MAC/LL) with scheduled channel access, a MAC/LL function without processor circuitry intervention, wherein the steady-state is a state that is control packet transmission free for managed connections in connection oriented communications or a continuous broadcast or scan operation in connectionless communications.