Patents by Inventor Bernard E. Weir, III

Bernard E. Weir, III has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5563594
    Abstract: A data conversion circuit receives input data from external sourcing logic and performs a parallel-serial conversion. Likewise, a data conversion circuit performs a serial-parallel conversion and presents output data to external sinking logic. In the parallel-serial conversion (10), the input data is translated (12) and stored in a register (14). A multiplexer (16) rotates through the data to provide the serial output. In the serial-parallel conversion (70), the input data is sequenced into a multiplexer (74) to achieve the parallel data word. The parallel data word is stored in a register (76) before presenting it to external logic. Phase delay logic (22) sets the delay of a transfer data control signal that requests data be read or written.
    Type: Grant
    Filed: August 31, 1994
    Date of Patent: October 8, 1996
    Assignee: Motorola
    Inventors: David K. Ford, Bernard E. Weir, III
  • Patent number: 5548285
    Abstract: A parallel to serial converter (10) uses a data hold-time indicator (22) to indirectly observe the timing relationship of the data and clock applied to a data register (14) embedded within an integrated circuit. The incoming data word is converted from CMOS to ECL logic levels (12) and applied to the data register. The register holds data for a multiplexer (16) that rotates through the output data from the register for providing a serial data output signal. A flipflop circuit (18) clocks the serial data output signal. The data hold-time indicator circuit monitors one register input and generates a recurring pulse having a width that reflects the data hold-time at the embedded register. By indirectly observing the timing relationship, the externally sourced data timing can be calibrated to meet the setup and hold-time requirements of the data register.
    Type: Grant
    Filed: July 18, 1994
    Date of Patent: August 20, 1996
    Assignee: Motorola, Inc.
    Inventors: David K. Ford, Bernard E. Weir, III
  • Patent number: 5309019
    Abstract: A low inductance lead frame (10) is formed to have a die attach area (11). A plurality of intermediate connection bars (12,13,14,15) are positioned to be parallel to sides of the die attach area (11), and to be in a plane that is displaced perpendicularly from the die attach area (11). Each end of each intermediate connection bar is separated from an end of each other intermediate connection bar. Supports (17) extend from the die attach area (11) to the intermediate connection bars (12,13,14,15) to provide support for the intermediate connection bars 12,13,14,15). A plurality of leads (19,33,34) are positional in a plane and have a proximal end near the intermediate connection bars (12,13,14,15).
    Type: Grant
    Filed: February 26, 1993
    Date of Patent: May 3, 1994
    Assignee: Motorola, Inc.
    Inventors: Daniel D. Moline, Bernard E. Weir, III