Patents by Inventor Bernard F. Phlips

Bernard F. Phlips has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10473692
    Abstract: A method of calibrating a topography metrology instrument using a calibration reference, which includes a substrate and a plurality of bi-layer stacks. Each bi-layer stack includes a plurality of bi-layer steps. At least one bi-layer step of the plurality of bi-layer steps includes two materials. The at least one bi-layer step of the plurality of bi-layer steps includes an etch stop layer and a bulk layer. The calibration reference includes a calibration reference step profile includes a plurality of predetermined bi-layer stack heights. The calibration reference step profile and the predetermined bi-layer stack heights are measured using a topography metrology instrument. The topography metrology instrument is calibrated based on the measured calibration reference step profile and the measured bi-layer stack heights.
    Type: Grant
    Filed: September 22, 2015
    Date of Patent: November 12, 2019
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips, Andrew J. Boudreau, Michael K. Yetzbacher
  • Patent number: 9997555
    Abstract: A device includes a surface profile optical element, including a substrate and a plurality of bi-layer stacks on the substrate. Each bi-layer stack of the plurality of bi-layer stacks includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch-stop layer and a bulk layer. The etch stop layer includes an etch stop layer index of refraction. The bulk layer includes a bulk layer index of refraction. A ratio of the etch stop layer index of retraction and the bulk layer index of refraction is between 0.75 and 1.25.
    Type: Grant
    Filed: May 17, 2017
    Date of Patent: June 12, 2018
    Assignee: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips, Michael K. Yetzbacher
  • Publication number: 20180040654
    Abstract: A device includes a surface profile optical element, including a substrate and a plurality of bi-layer stacks on the substrate. Each bi-layer stack of the plurality of bi-layer stacks includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch-stop layer and a bulk layer. The etch stop layer includes an etch stop layer index of refraction. The bulk layer includes a bulk layer index of refraction. A ratio of the etch stop layer index of retraction and the bulk layer index of refraction is between 0.75 and 1.25.
    Type: Application
    Filed: May 17, 2017
    Publication date: February 8, 2018
    Inventors: Marc Christophersen, Bernard F. Phlips, Michael K. Yetzbacher
  • Publication number: 20160091703
    Abstract: A method of calibrating a topography metrology instrument using a calibration reference, which includes a substrate and a plurality of bi-layer stacks. Each bi-layer stack includes a plurality of bi-layer steps. At least one bi-layer step of the plurality of bi-layer steps includes two materials. The at least one bi-layer step of the plurality of bi-layer steps includes an etch stop layer and a bulk layer. The calibration reference includes a calibration reference step profile includes a plurality of predetermined bi-layer stack heights. The calibration reference step profile and the predetermined bi-layer stack heights are measured using a topography metrology instrument. The topography metrology instrument is calibrated based on the measured calibration reference step profile and the measured bi-layer stack heights.
    Type: Application
    Filed: September 22, 2015
    Publication date: March 31, 2016
    Inventors: Marc Christophersen, Bernard F. Phlips, Andrew J. Boudreau, Michael K. Yetzbacher
  • Patent number: 9128192
    Abstract: Caesium-137 irradiates electronic paper. An incoming gamma-ray from the Cs-137 interacts with a particle inside a micro-container by generating a recoil electron and/or a hole. Because the recoil electron physically leaves the particle, the particle is charged depending on the dose from the radiation source. And, the charge of the particles change, which results in a movement of the particles within the micro-container. After refreshing the electronic paper, a visible difference in the gray-scale can be seen. Thus, the visible difference in the gray-scale is an effect caused by the irradiation of the electronic paper, showing sensitivity to high energy radiation—thus, non-optimized electronic paper is sensitive to high energy radiation and can be used as a radiation dosimeter. In addition, electronic paper can be used for sensing chemical and bio-chemical agents, as well as detecting high energy radiation.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: September 8, 2015
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Patent number: 9035408
    Abstract: A ramped etalon cavity structure and a method of fabricating same. A bi-layer stack is deposited on a substrate. The bi-layer stack includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch stop layer and a bulk layer. A three dimensional photoresist structure is formed by using gray-tone lithography. The three dimensional photoresist is plasma etched into the bi-layer stack, thereby generating an etched bi-layer stack. The etched bi-layer stack is chemically etched with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: May 19, 2015
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Andrew J. Boudreau, Michael K. Yetzbacher, Marc Christophersen, Bernard F. Phlips
  • Patent number: 8932894
    Abstract: Gray tone lithography is used to form curved silicon topographies for semiconductor based solid-state imaging devices. The imagers are curved to a specific curvature and shaped directly for the specific application; such as curved focal planes. The curvature of the backside is independent from the front surface, which allows thinning of the detector using standard semiconductor processing.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: January 13, 2015
    Assignee: The United States of America, as represented by the Secratary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Publication number: 20140327099
    Abstract: A ramped etalon cavity structure and a method of fabricating same. A bi-layer stack is deposited on a substrate. The bi-layer stack includes a plurality of bi-layers. Each bi-layer of the plurality of bi-layers includes an etch stop layer and a bulk layer. A three dimensional photoresist structure is formed by using gray-tone lithography. The three dimensional photoresist is plasma etched into the bi-layer stack, thereby generating an etched bi-layer stack. The etched bi-layer stack is chemically etched with a first chemical etchant to generate a multiple-step structure on the substrate, wherein the first chemical etchant stops at the etch stop layer.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 6, 2014
    Inventors: Andrew J. Boudreau, Michael K. Yetzbacher, Marc Christophersen, Bernard F. Phlips
  • Patent number: 8841170
    Abstract: A method of singulating semiconductor devices in the close proximity to active structures by controlling interface charge of semiconductor device sidewalls is provided that includes forming a scribe on a surface of a semiconductor devices, where the scribe is within 5 degrees of a crystal lattice direction of the semiconductor device, cleaving the semiconductor device along the scribe, where the devices are separated, using a coating process to coat the sidewalls of the cleaved semiconductor device with a passivation material, where the passivation material is disposed to provide a fixed charge density at a semiconductor interface of the sidewalls, and where the fixed charge density interacts with charge carriers in the bulk of the material.
    Type: Grant
    Filed: October 21, 2011
    Date of Patent: September 23, 2014
    Assignees: The Regents of the University of California, Naval Research Laboratory
    Inventors: Vitaliy Fadeyev, Hartmut F. W. Sadrozinski, Marc Christophersen, Bernard F. Phlips
  • Publication number: 20130203239
    Abstract: A method of singulating semi-conductor devices in the close proximity to active structures by controlling interface charge of semiconductor device sidewalls is provided that includes forming a scribe on a surface of a semi-conductor devices, where the scribe is within 5 degrees of a crystal lattice direction of the semi-conductor device, cleaving the semiconductor device along the scribe, where the devices are separated, using a coating process to coat the sidewalls of the cleaved semiconductor device with a passivation material, where the passivation material is disposed to provide a fixed charge density at a semiconductor interface of the sidewalls, and where the fixed charge density interacts with charge carriers in the bulk of the material.
    Type: Application
    Filed: October 21, 2011
    Publication date: August 8, 2013
    Inventors: Vitaliy Fadeyev, Hartmut F.W. Sadrozinski, Marc Christophersen, Bernard F. Phlips
  • Patent number: 8481953
    Abstract: Radiation detectors can be made of n-type or p-type silicon. All segmented detectors on p-type silicon and double-sided detectors on n-type silicon require an “inter-segment isolation” to separate the n-type strips from each other; an alumina layer for isolating the strip detectors is applied, and forms negative charges at the silicon interface with appropriate densities. When alumina dielectric is deposited on silicon, the negative interface charge acts like an effective p-stop or p-spray barrier because electrons are “pushed” away from the interface due to the negative interface charge.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: July 9, 2013
    Assignee: The United States of America, as represented by the Secretary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Publication number: 20120193551
    Abstract: Caesium-137 irradiates electronic paper. An incoming gamma-ray from the Cs-137 interacts with a particle inside a micro-container by generating a recoil electron and/or a hole. Because the recoil electron physically leaves the particle, the particle is charged depending on the dose from the radiation source. And, the charge of the particles change, which results in a movement of the particles within the micro-container. After refreshing the electronic paper, a visible difference in the gray-scale can be seen. Thus, the visible difference in the gray-scale is an effect caused by the irradiation of the electronic paper, showing sensitivity to high energy radiation--thus, non-optimized electronic paper is sensitive to high energy radiation and can be used as a radiation dosimeter. In addition, electronic paper can be used for sensing chemical and bio-chemical agents, as well as detecting high energy radiation.
    Type: Application
    Filed: February 2, 2011
    Publication date: August 2, 2012
    Applicants: Counsel
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Publication number: 20120161266
    Abstract: Radiation detectors can be made of n-type or p-type silicon. All segmented detectors on p-type silicon and double-sided detectors on n-type silicon require an “inter-segment isolation” to separate the n-type strips from each other; an alumina layer for isolating the strip detectors is applied, and forms negative charges at the silicon interface with appropriate densities. When alumina dielectric is deposited on silicon, the negative interface charge acts like an effective p-stop or p-spray barrier because electrons are “pushed” away from the interface due to the negative interface charge.
    Type: Application
    Filed: February 29, 2012
    Publication date: June 28, 2012
    Applicants: Counsel
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Patent number: 8008626
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Grant
    Filed: January 21, 2011
    Date of Patent: August 30, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J Kub, Bernard F Phlips, Karl D Hobart, Eric A Wulf
  • Patent number: 7968959
    Abstract: Gray-tone lithography technology is used in combination with a reactive plasma etching operation in the fabrication method and system of a thick semiconductor drift detector. The thick semiconductor drift detector is based on a trench array, where the trenches in the trench array penetrate the bulk with different depths. These trenches form an electrode. By applying different electric potentials to the trenches in the trench array, the silicon between neighboring trenches fully depletes. Furthermore, the applied potentials cause a drifting field for generated charge carriers, which are directed towards a collecting electrode.
    Type: Grant
    Filed: October 19, 2009
    Date of Patent: June 28, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Publication number: 20110127527
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Application
    Filed: January 21, 2011
    Publication date: June 2, 2011
    Applicant: The Government of the United States of America, as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Bernard F. Phlips, Karl D. Hobart, Eric A. Wulf
  • Patent number: 7902513
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Grant
    Filed: March 18, 2009
    Date of Patent: March 8, 2011
    Assignee: The United States of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Bernard F. Phlips, Karl D. Hobart, Eric A. Wulf
  • Publication number: 20100264502
    Abstract: Gray tone lithography is used to form curved silicon topographies for semiconductor based solid-state imaging devices. The imagers are curved to a specific curvature and shaped directly for the specific application; such as curved focal planes. The curvature of the backside is independent from the front surface, which allows thinning of the detector using standard semiconductor processing.
    Type: Application
    Filed: October 19, 2009
    Publication date: October 21, 2010
    Applicant: US Gov't Represented by the Secretary of the Navy Office of Naval Research (ONR/NRL) code OOCCIP
    Inventors: Marc Christophersen, Bernard F. Phlips
  • Publication number: 20100213380
    Abstract: A silicon-on-insulator (SOI) neutron detector comprising a silicon-on-insulator structure, wherein the silicon-on-insulator structure consists of an active semiconductor layer, a buried layer, and a handle substrate, a lateral carrier transport and collection detector structure within the active semiconductor layer of the silicon-on-insulator structure, and a neutron to high energy particle converter layer on the active semiconductor layer.
    Type: Application
    Filed: March 18, 2009
    Publication date: August 26, 2010
    Applicant: The Government of the United State of America as represented by the Secretary of the Navy
    Inventors: Francis J. Kub, Bernard F. Phlips, Karl D. Hobart, Eric A. Wulf
  • Publication number: 20100096674
    Abstract: Gray-tone lithography technology is used in combination with a reactive plasma etching operation in the fabrication method and system of a thick semiconductor drift detector. The thick semiconductor drift detector is based on a trench array, where the trenches in the trench array penetrate the bulk with different depths. These trenches form an electrode. By applying different electric potentials to the trenches in the trench array, the silicon between neighboring trenches fully depletes. Furthermore, the applied potentials cause a drifting field for generated charge carriers, which are directed towards a collecting electrode.
    Type: Application
    Filed: October 19, 2009
    Publication date: April 22, 2010
    Inventors: Marc Christophersen, Bernard F. Phlips