Abstract: The demodulator therefore features a multiplexer connected to the different transmission channels. The output of the multiplexer is connected to a sampler-coder, followed by an interpolator, which is itself followed by a phase jump converter and a statistical decision device validating the code conversion result, when a certain number of samples taken in a series of successive samples have a phase jump in the same range of values.

Abstract: The words to be added together by the high-speed sequential adder are stored in shift registers 1.sub.l to 1.sub.p whose serial outputs are connected to the corresponding inputs of a transcoder 2 producing the binary number of "1's" for each bit weight of the words to be added. This value is sent to an adder-divider 4 which adds it to the number of carried "1's" from the immediately lesser weight and divides this sum by 2, sending the fractional part of this half-sum to an output register 5 and the whole-number part to a carry register.Application: digital filters for PCM telephone switching.

Abstract: A digital filter for shared-time processing on several channels. The filter has several elementary cells (C.sub.1 to C.sub.K), each comprising a read-write memory (M.sub.1 to M.sub.K), a read-only memory (H.sub.1 to H.sub.K), and an arithmetic unit (U.sub.1 to U.sub.K). A page address counter CT.sub.1, a word address counter CT.sub.2 and a weighting coefficient address counter CT.sub.3 are common to the cells. Delayed discrete values are transferred by the relative addressing of the memory words. The filter will find particular application as a half-band extrapolator filter for telephone switching.