Abstract: An electrically erasable and reprogrammable non volatile memory cell is disclosed which is implemented in CMOS polycrystalline silicon gate transistor technology and comprises a p-channel MOS transistor the gate of which forms a first portion of a floating electrode. A second portion of said floating electrode has a substantially larger surface than the two other portions and is placed on a field oxide layer. A third portion of the floating electrode is placed on an injection oxide layer which is thinner than the gate oxide layer of the transistor. A p.sup.- -doped well is formed under said third portion and is connected electrically to a write control electrode. An erase control electrode is arranged opposite the second portion of the floating electrode. The disclosed memory cell can be erased and reprogrammed through relatively low control voltages of a single polarity and these processes lead only to very small current consumption.

Abstract: The invention relates to non-volatile electrically erasable and reprogrammable memories produced by CMOS technology.According to the invention, each memory element comprises only a single p-channel transistor having a polycrystalline silicon floating gate capacitively coupled to a control electrode. The thicknesses of injection oxide and gate oxide are such that the element can be programmed by avalanche of the drain-substrate junction and erased by field emission of electrons from the floating gate towards the substrate.All the voltages required can be generated on the circuit of the memory from a battery voltage of 1.5 volts.

Abstract: A reference voltage source implemented in silicon-gate CMOS transistor technology comprises a pair of reference transistors of the same conductivity type, the gates of which are made of polycrystalline silicon and differ from each other by the type of doping. The reference voltage can be temperature-compensated by adding an auxiliary compensation voltage source or by establishing a predetermined ratio of current densities in the pair of reference transistors operating in weak inversion.

Abstract: An electrically reprogrammable non-volatile memory device is disclosed which includes complementary MOS transistors provided with a polycrystalline silicon floating gate electrode in a common n.sup.- -type substrate. The device comprises three main parts. The first part, which is used for writing, comprises a p-channel writing transistor, a p-channel control transistor and a resistance element. The second part, which comprises a second gate electrode capacitance coupled with the floating gate, is used for erasing. The third part is used for performing information read-out and consists of a p-channel transistor the gate of which forms a portion of the floating gate and the drain of which is connected to a read-out terminal and to the terminal of a loading element having its other terminal connected to a negative supply potential.

Abstract: An integrated circuit comprises complementary FET having channels extending on the surface of a substrate and on the surface of a well in the substrate and gates formed in a layer of polycrystalline silicon insulated from the substrate and from each said well. A floating diode, i.e. connected neither to the substrate, nor to a well, is formed simultaneously with the FET by depositing and selectively etching a first doped oxide to cover a first region of the polycrystalline silicon, depositing an oppositely doped oxide over the remainder using the first oxide as mask, and oppositely doping the two regions of polycrystalline silicon by heat treatment. Alternatively, the second region can be doped by treatment in a gaseous phase or by ionic implantation, in either case using the first oxide as mask.