Abstract: An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole.

Abstract: An interface includes a surface having an electrically conductive pad; a compliant coating over the surface having a via extending to the pad; metallization patterned over the compliant coating and extending into the via; a low modulus dielectric interface layer overlying the compliant coating and having an interface via extending to the metallization; and a floating pad structure including floating pad metallization patterned over the dielectric interface layer with a first portion forming a central pad and a second portion forming an extension from the central pad extending into the interface via. Another interface includes a substrate including a low modulus dielectric interface material having a hole extending at least partially therethrough and a floating contact structure including electrically conductive material coating the hole with at least some of the floating pad metallization forming an extension from the hole.

Abstract: A capacitor is fabricated on a base surface by applying a first pattern of electrical conductors (a first capacitor plate) over the base surface with an outer surface of the first pattern of electrical conductors including molybdenum. A first hard portion of a capacitor dielectric layer including amorphous hydrogenated carbon is deposited over the first capacitor plate and the base surface, a soft portion of the capacitor dielectric layer is deposited over the first hard portion, and a second hard portion of the capacitor dielectric layer is deposited over the soft portion. The deposition of the soft portion occurs at a lower bias voltage than the deposition of the first and second hard portions. A second pattern of electrical conductors (a second capacitor plate) is applied over the capacitor dielectric layer which is then patterned.

Abstract: Connection elements which, for example, may be used to facilitate interconnection to and stacking of electronic assemblies or may include an elongated conductive core, such as a wire or a hollow tube structure, coated with a layer of elastomeric material containing conductive particle such that the elastomeric material is conductive at least when compressed. The substrates of multi-chip modules (MCMs) have electrical connection sites in the form of metal-lined channels in the substrate edges, and the connection elements are pressed into the channels. Separate compression or clamping elements may be employed to enhance conductivity, as well as to facilitate external connections. The elongated conductive core may take the form of a hollow tube structure which may be expanded under internal pressure to compress the layer of elastomeric material. The compression elements may take the form of printed circuit boards.

Abstract: A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.

Abstract: A capacitor is fabricated on a base surface by applying a first pattern of electrical conductors (a first capacitor plate) over the base surface with an outer surface of the first pattern of electrical conductors including molybdenum. A first hard portion of a capacitor dielectric layer including amorphous hydrogenated carbon is deposited over the first capacitor plate and the base surface, a soft portion of the capacitor dielectric layer is deposited over the first hard portion, and a second hard portion of the capacitor dielectric layer is deposited over the soft portion. The deposition of the soft portion occurs at a lower bias voltage than the deposition of the first and second hard portions. A second pattern of electrical conductors (a second capacitor plate) is applied over the capacitor dielectric layer which is then patterned.

Abstract: A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates.

Abstract: A method for fabricating a stack of circuit modules includes providing a plurality of substrates having module interconnection layers. Each of the substrates has a circuit chip with chip pads positioned therein and an electrically conductive feed-through line extending from a first surface of the substrate to a second surface of the substrate with the first surface being perpendicular to the second surface. Each of the module interconnection layers is situated over a respective first surface of each of the substrates and includes a module dielectric layer having module vias therein and a module pattern of electrical conductors extending through the module vias to couple the selected chip pads to the feed-through line. The plurality of substrates are stacked. A side interconnection layer is applied over a side surface including the second surfaces of the substrates.

Abstract: A flexible, multilayer thin film capacitor comprises a flexible substrate and at least two electrode layers mounted on the substrate alternately with at least one dielectric layer. The dielectric layer may include amorphous hydrogenated carbon. The at least two electrode layers and the at least one dielectric layer are capable of acting as at least one capacitor, and the flexible substrate is capable of being manipulated so as to have a desired shape.

Abstract: A protective cap is deposited over the top and sides of an air bridge structure located on an integrated circuit chip. The protective cap provides mechanical strength during the application of a high density interconnect structure over the chips, to prevent deformation of the sensitive (air bridge) structure, and also to prevent any contamination from intruding under the air bridge. More importantly, the protective cap does not impede the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure. Furthermore, the protective cap allows additional area for metallization to provide alternate circuits for coupling, power or ground planes, etc.

Abstract: A method for fabricating a circuit module includes applying an outer insulative layer over a first patterned metallization layer on a first surface of a base insulative layer. A second surface of the base insulative layer has a second patterned metallization layer. At least one circuit chip having chip pads is attached to the second surface of the base insulative layer. Respective vias are formed to expose selected portions of the first patterned metallization layer, the second patterned metallization layer, and the chip pads. A patterned outer metallization layer is applied over the outer insulative layer to extend through selected ones of the vias to interconnect selected ones of the chip pads and selected portions of the first and second metallization layers.

Abstract: In a method for preserving an air bridge structure on an integrated circuit chip, a protective layer is plasma-deposited over the top and sides of the air bridge. A high density interconnect structure is applied over the chip and protective layer. The protective film provides mechanical strength during the application of the high density interconnect structure to prevent deformation. It also prevents any contamination from intruding under the air bridge. More importantly, the protective film only negligibly impedes the performance of the air bridge and therefore does not need to be removed, thereby eliminating the necessity of ablating the HDI structure.

Abstract: In a method for preserving an air bridge structure on an integrated circuit chip used in an overlay process, a patternable protective layer is applied for providing mechanical strength to prevent deformation during subsequent processing. A polymeric film layer is applied over the chip and protective layer, and interconnections are fabricated through the polymeric film layer. The polymeric film layer is removed from the area over the air bridge structure. The patternable protective layer is then removed, leaving the resultant structure with an undamaged air bridge which is free of residue.

Abstract: Semiconductor device contact pads are enhanced by forming a metal plate over at least a portion of the contact pad. "Enhancement" includes repair such as by bridging a reinforcing pad area over probe damage, general reinforcement or enlargement of a contact pad, and placement of a protective buffer pad over a contact pad. These methods are applicable to any semiconductor device with contact pads on a surface thereof, such as entire wafers, individual dice, and multi-chip High Density Interconnect (HDI) modules. The pad enhancement plate is formed by applying a planarizing dielectric layer over the entire device (if not already formed in the initial stages of HDI processing), and an enhancement access via is then formed to expose a portion of the contact pad to be enhanced. The entire device is metallized, and metal not over the exposed portion of the contact pad is subsequently removed.

Abstract: In fabricating wafer scale integrated interconnects, a temporary or permanent dielectric layer and a pattern of electrical conductors are used to provide wafer scale integration or testing and burn-in. A resist can be used to cover the areas of IC pads on the wafer while the remainder of the pattern of electrical conductors is removed to provide for repair of the wafer scale integration structure. The pattern of electrical conductors may be configured so that the conductor lengths between at least some sub-circuits on a plurality of wafers are substantially electrically equal for signal propagation purposes; an additional wafer may be laminated to the wafer using an adhesive; controlled curfs may be cut into the wafer; and the wafer may be interconnected to an interface ring.

Abstract: Combustion in a gas turbine is controlled through use of flame spectroscopy in order to achieve low NO.sub.x emissions in the exhaust. By monitoring the combustion flame in the turbine to determine intensity of non-infrared spectral lines, and dynamically adjusting the fuel/air ratio of the fuel mixture such that this intensity remains below a predetermined level associated with a desired low level of NO.sub.x emissions, the engine produces significantly reduced NO.sub.x emissions in its exhaust but at a sufficiently high combustion flame temperature to avoid any undue risk of flame-out, thereby assuring stable, safe and reliable operation.

Abstract: A method for fabricating a metal interconnection pattern for an integrated circuit module is provided comprising the steps of: aligning only one face of the module, forming a metal layer on at least one other face of the module, applying a coating of photoresist to the metal layer, exposing predetermined portions of the photoresist to reflected radiation, and shaping the metal layer in accordance with the exposed photoresist portions.

Abstract: Combustion in a gas turbine is controlled through use of flame spectroscopy in order to achieve low NO.sub.x emissions in the exhaust. By monitoring the combustion flame in the turbine to determine intensity of non-infrared spectral lines, and dynamically adjusting the fuel/air ratio of the fuel mixture such that this intensity remains below a predetermined level associated with a desired low level of NO.sub.x emissions, the engine produces significantly reduced NO.sub.x emissions in its exhaust but at a sufficiently high combustion flame temperature to avoid any undue risk of flame-out, thereby assuring stable, safe and reliable operation.

Abstract: A multi-cellular power field effect semiconductor device includes a high conductivity layer of metal or a metal silicide disposed in intimate contact with the source region of the device. This high conductivity layer is self-aligned with respect to the aperture in the gate electrode through which the source region is diffused. The presence of this high conductivity layer allows a substantially smaller contact window to be employed for making contact between the final metallization and the source region. As a consequence, the aperture in the gate electrode and the cell size of the device can both be substantially reduced. The device has substantially improved operating characteristics. A method of producing the device is also described.

Abstract: A contact metal such as tungsten, platinum silicide or palladium silicide is selectively deposited or formed on the semiconductor substrate portion of an integrated circuit chip. The metallization pattern for the circuit makes contact with the contact metal at the bottom of a contact opening or via, rather than contacting the substrate directly. Thus, the interconnection metal makes contact to the semiconductor surface through an intermediate contact metal so as to provide decreased contact resistance. This permits narrower interconnect metallization patterns so as to facilitate the construction of denser integrated circuits. In the present invention, therefore, metal framing of the contact hole is not employed.