Patents by Inventor BERNARD KAEBIN ANDRES ANCHETA

BERNARD KAEBIN ANDRES ANCHETA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11862479
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Grant
    Filed: June 23, 2021
    Date of Patent: January 2, 2024
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • Publication number: 20220149003
    Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.
    Type: Application
    Filed: January 25, 2022
    Publication date: May 12, 2022
    Inventors: RONALDO MARASIGAN ARGUELLES, EDGAR DOROTAYO BALIDOY, GLORIA BIBAL MANAOIS, BERNARD KAEBIN ANDRES ANCHETA
  • Patent number: 11233031
    Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: January 25, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Ronaldo Marasigan Arguelles, Edgar Dorotayo Balidoy, Gloria Bibal Manaois, Bernard Kaebin Andres Ancheta
  • Publication number: 20210320014
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Application
    Filed: June 23, 2021
    Publication date: October 14, 2021
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • Patent number: 11081366
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Grant
    Filed: December 5, 2018
    Date of Patent: August 3, 2021
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • Publication number: 20200185234
    Abstract: A method of making a semiconductor device includes mounting at least two semiconductor dies to a die pad of a leadframe in spaced apart relation to each other, the leadframe having a plurality of preformed leads, electrically connecting each semiconductor die to at least one preformed lead of the leadframe, forming a molding structure including at least part of the semiconductor dies and the preformed leads of the leadframe, and forming a trench in the molding structure in a space between the at least two semiconductor dies, the trench separating the die pad into first and second die pad portions.
    Type: Application
    Filed: December 5, 2018
    Publication date: June 11, 2020
    Inventors: Bernard Kaebin Andres Ancheta, Emerson Mamaril Enipin, John Carlo Cruz Molina
  • Publication number: 20170170101
    Abstract: A flip-chip on leadframe package includes a leadframe having a plurality of leads with each lead including an inner leadfinger portion, wherein at least a landing region of all of the inner leadfinger portions are in a single common level (or plane) and include etched areas providing bump pads having concave landing sites (landing sites). A semiconductor die (die) having an active top side surface with functional circuitry including bond pads has bumps or pillars thereon. An area of the landing sites is greater than an area of the bumps or pillars. A distal end of the bumps or pillars is within and electrically coupling to the landing sites. A mold material encapsulates the die and at least a portion of the inner leadfinger portions. The package can be a leaded package or a leadless package.
    Type: Application
    Filed: December 9, 2015
    Publication date: June 15, 2017
    Inventors: RONALDO MARASIGAN ARGUELLES, EDGAR DOROTAYO BALIDOY, GLORIA BIBAL MANAOIS, BERNARD KAEBIN ANDRES ANCHETA