Abstract: A system for transmitting digital information, especially on an optical link, comprises a send end unit and a receive end unit. It includes a device for evaluating the bit error rate at the receiving end and a device for controlling one or more characteristic parameters of the send end unit and/or the receive end unit according to the evaluated bit error rate and in such a way as continuously to optimize the parameter(s) in the light of the actual performance of the transmission system.

Abstract: The method enables transmission of a digital service channel by means of the parity channel of a digital bit stream transmitted in a parity checking code with parity words inserted at specific times by modifying certain parity words violating the parity checking code parity law. It consists in modifying spaced groups of even number of consecutive parity words so as not to disrupt analog detection of line errors. A digital service channel insertion circuit is included among the component parts of an MBIPIC type encoder whereby the data of a digital bit stream is transmitted by consecutive code words each formed of a block of data bits completed by a parity bit and an inversion bit.

Abstract: A detector logic circuit restores the value 0 or .+-.1 of a ternary symbol converted into a signal on five levels 0, .+-.1 and .+-.2 as a result of class 1, type n=2 partial response transmission. Employing only binary logic circuits, it is connected to the output of a comparator which has four thresholds and which delivers a value representing the receive level by four binary signals. Two of these signals indicate positive overshooting of extreme and intermediate positive thresholds. The other two indicate negative overshooting of negative extreme and intermediate thresholds. The circuit delivers the values of the ternary symbols detected in the form of two binary components which are available at the output and stored for the duration of a symbol by two flip-flops. Both are generated by combinational logic devices of similar design utilizing OR and NOR gates.

Abstract: A synchronous digital cable transmission system comprises a transmitting terminal, intermediate regenerative repeaters and a receiving terminal. The transmitting terminal includes a data scrambler and a 6B/4T type binary-ternary line coder. The receiving terminal and the intermediate regenerated repeaters include a class 1 type n=2 partial response coding type receive signal shaping and filtering unit and a logic device for decrypting binary symbol superpositions resulting from the signal shaping and filtering processes. The receiving terminal also includes a 6B/4T binary-ternary decoder and a descrambler respectively compatible with the coder and the scrambler in the transmitting terminal.

Abstract: A synchronous data transmission method uses an MB 1C 1F type binary-binary code in which the binary data to be transmitted is subdivided into successive blocks of M bits complemented when they feature a disparity (marks minus spaces) of the same sign as the data already encoded, to which is added a complement bit indicating if complementing has been applied and a frame bit consisting of a parity bit enabling the subdivision into blocks carried out at the encoding stage to be recovered at the decoding stage. The encoder has at the input a demultiplexer carrying out the subdivision into blocks followed by circuits for computing the word digital sum and parity and the running digital sum, together with an inverter circuit which processes the blocks from the multiplexer and their parity bit under the control of a complementing decision circuit and a multiplexer transforming the encoded binary signal from the inverter circuit into an isochronous sequence to which a frame bit is added.

Abstract: Demodulator assembly for m data trains, with differential phase modulation, comprising, for each train, an elementary demodulator dimensioned over a space of one bit, whereas the coding is effected over a space of n intermediate bits, comprising, for each train, a shift register having n+1 flip-flops in a functional connection with an adder.