Abstract: A low voltage CMOS output buffer protection circuit is configured to protect an associated output buffer from any high voltage signals (e.g., 5V) that may appear along a signal bus line. The protection circuit is also "hot-pluggable", meaning that the protection circuit will not draw any current when not powered (i.e., when VDD is not present). An on-chip reference voltage generator is used to provide a reference voltage VDD2 that will be essentially equal to VDD as long as VDD is present. When VDD is not present, VDD2 will track the signal appearing along the signal bus (PAD), remaining at least two diode drops below the PAD voltage.

Abstract: An integrated circuit output buffer has an improved tolerance to voltage levels that are greater than the power supply voltage level at which the IC is designed to operate. A first transmission gate transistor (110), typically p-channel, is connected between an output conductor (101) and a resistor (108) at a given node (114). The node is also connected to the gate of a second transmission gate transistor (105), typically also p-channel. The resistor pulls the given node towards a power supply voltage level (e.g., ground), so that the second transmission gate transistor conducts in normal operation. To prevent the node from reaching ground, at least one diode-like voltage-dropping device (201, 202) is connected in series with the resistor.

Abstract: A differential comparison circuit obtains an improved common mode range with respect to the voltages on first and second inputs. A first comparator is activated when the first and second input voltages are above a first level. A second comparator is activated when the first and second input voltages are below a second level. The output of the comparator that is activated is selected for providing the comparison output signal. In this manner, the comparator having improved performance, typically in terms of differential input voltage sensitivity, may be selected for the voltages present at the inputs. In a typical embodiment, the first comparator uses n-channel input devices, and the second comparator uses p-channel input devices. The activation is provided by voltage level-sensing circuitry, and may include hysteresis to help ensure reliable operation.

Abstract: An integrated circuit output buffer that is fabricated using a relatively low voltage technology is capable of driving a relatively high voltage swing to an output conductor. For example, a buffer implemented in 3.3 volt CMOS technology can deliver a 5 volt output swing. This is achieved by scaling up the output voltage swings from the lower voltage level to the higher voltage level using one or more intermediate inverters that operate at successively higher voltage levels. In a preferred embodiment, the voltage levels are provided using a power conservation circuit that limits current flow through a resistor voltage divider network.

Abstract: A communication system having communicating devices coupled to a closed loop bus substantially reduces interconnect distances and corresponding signal propagation delays between the devices. Particular devices possess switchable impedance elements that can be selectively actuated to produce an effective terminating impedance substantially at a midpoint position along the closed loop from the coupling point of a transmission device. In such an arrangement, the produced effective terminating impedance would cause the signal transmitted by the transmission device to propagate to a destination device substantially without signal degradation due to signal reflections.