Abstract: A method and circuit for lowering impedance of a transistor bridge having two pairs of cooperating transistors, comprising receiving a pair of DC input signals which enable activation of one of the pairs of transistors, the activation providing a path for the DC input signals through the two activated transistors, the pair of DC input signals having voltages differing from each other by a first amount; and applying a second pair of DC signals each to a different gate of the two activated transistors, the second pair of DC signals having voltages differing from each other by a second amount that is greater than the first amount, wherein as a result of the second amount being greater than the first amount, impedances of the two activated transistors are lower as compared to if the pair of DC input signals were used in substitution for the second pair of signals.

Abstract: A low impedance polarity conversion circuit for driving a load with a DC power source is disclosed. The DC power source has a first pole from which a first DC signal originates and a second pole from which a second DC signal originates. The first DC signal has a voltage greater than a voltage of the second DC signal. The conversion circuit includes a circuit output node through which an output DC signal is delivered from the conversion circuit to the load. The conversion circuit also includes a charge conditioning circuit for generating third and fourth DC signals. The third DC signal has a voltage greater than the first DC signal voltage and the fourth DC signal has a voltage less than the second DC signal voltage. A rectification circuit includes first and second inputs for attachment to the first pole and the second pole. A Field-Effect Transistor (FET) bridge is electrically connected to the first and second inputs. The FET bridge includes first and second pairs of cooperating FETs.

Abstract: A low impedance polarity conversion circuit for driving a load with a DC power source is disclosed. The DC power source has a first pole from which a first DC signal originates and a second pole from which a second DC signal originates. The first DC signal has a voltage greater than a voltage of the second DC signal. The conversion circuit includes a circuit output node through which an output DC signal is delivered from the conversion circuit to the load. The conversion circuit also includes a charge conditioning circuit for generating third and fourth DC signals. The third DC signal has a voltage greater than the first DC signal voltage and the fourth DC signal has a voltage less than the second DC signal voltage. A rectification circuit includes first and second inputs for attachment to the first pole and the second pole. A Field-Effect Transistor (FET) bridge is electrically connected to the first and second inputs. The FET bridge includes first and second pairs of cooperating FETs.