Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.

Abstract: A cryptographic system comprising: 1) a first Montgomery-based cryptographic engine that receives a first operand and a second operand and generates a first result and 2) a second Montgomery-based cryptographic engine that receives a first reduced operand derived from the first operand and a second reduced operand derived from the second operand and generates a second result. The second Montgomery-based cryptographic engine operates in parallel with the first Montgomery-base cryptographic engine. The cryptographic system further comprises a comparator for comparing the second result to a first reduced result derived from the first result and generating an error flag if the second result and the first reduced result are different.

Abstract: An apparatus arranged to accept digital data as an input and to process the data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a plurality of rotational registers for storing data, one of the registers arranged to receive the input data, and data stores for initialization of some of the plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of the plurality of registers.

Abstract: An apparatus arranged to accept digital data as an input and to process the data according to one of either the Secure Hash Algorithm (SHA-1) or Message Digest (MD5) algorithm to produce a fixed length output word. The apparatus includes a plurality of rotational registers for storing data, one of the registers arranged to receive the input data, and data stores for initialization of some of the plurality of registers according to whether the SHA-1 or MD5 algorithm is used. The data stores include fixed data relating to SHA-1 and MD5 operation. Also included is a plurality of dedicated combinatorial logic circuits arranged to perform logic operations on data stored in selected ones of the plurality of registers.

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract: A circuit and a method are provided for securing a coprocessor dedicated to cryptography. The disclosed circuit includes a scrambling register and an accessory input register to convey scrambling information in the form of electrical signals that disturb the visibility of certain electrical signals associated with confidential information such as digital keys.

Abstract: A cryptographic system comprising: 1) a first Montgomery-based cryptographic engine that receives a first operand and a second operand and generates a first result and 2) a second Montgomery-based cryptographic engine that receives a first reduced operand derived from the first operand and a second reduced operand derived from the second operand and generates a second result. The second Montgomery-based cryptographic engine operates in parallel with the first Montgomery-base cryptographic engine. The cryptographic system further comprises a comparator for comparing the second result to a first reduced result derived from the first result and generating an error flag if the second result and the first reduced result are different.

Abstract: An apparatus and method for performing a modular operation S=AB mod N, the apparatus arranged such that the constant J0, which is ordinarily required in order to complete the operation, is not required to be explicitly computed, thus simplifying and speeding up the operation.

Abstract: In the field of systems for the synchronization of modular electronic circuits, a system is provided for the coordinated activation of the modules. This system includes synchronization cells that have their pace set by a primary clock signal and deliver secondary clock signals controlled intermittently by the enabling signals to respectively activate the modules. The cells lock the state of each enabling signal associated with a regulator for regulating the periodicity of the change in state of each secondary clock signal and coordinating the changes in states of the secondary clock signals with one another. The system can be advantageously applied to electronic circuits having very high frequency data processing modules, especially those providing for the multiplexing of the transmissions of data carried out by each module.

Abstract: A memory comprises at least one array of memory elements, a partition of the at least one array into a plurality of sub-arrays of the memory elements, and an array configuration circuit for selectively putting the at least one array in one of two operating configurations. In a first operating configuration, the memory elements of the at least one array are coupled one to another to form a monodimensional sequentially-accessible memory, while in a second operating configuration the memory elements in each sub-array are coupled to one another so as to form an independent monodimensional sequentially-accessible memory block, a data content of any memory element of the sub-array being rotatable by shifts through the memory elements of the sub-array. A sub-array selector, responsive to a first memory address, selects one among the at least two sub-arrays according to the first memory address, and enables access to the selected sub-array.

Abstract: A storage device is provided. The storage device includes at least one memory having a parallel data bus and a parallel address bus; a first k-bit latch circuit having a parallel input and a parallel output, with the parallel input being connected to the data bus; a first k-bit shift register having a parallel input and a series output, with the parallel input being connected to the output of the first latch circuit; a second k-bit latch circuit having a parallel input and a parallel output, with the parallel output being connected to the data bus; and a second k-bit shift register having a series input and a parallel output, with the parallel output being connected to the input of the second latch circuit. In a preferred embodiment, a control circuit is coupled to the address bus, with the control circuit including address registers for storing as many address pointers as the number of k-bit shift registers.

Abstract: A Pfield operation defined according to the Montgomery method by Pfield(A, B)N=A*B*I mod N, where I is a determinable error, is implemented in a processor. The least significant word of the data elements A and N which are stored in elementary sub-registers are shifted twice. This eliminates delay cells in a processor used for executing the Pfield operation.

Abstract: In an electronic component including a two-way bus through which data elements travel between peripherals and a central processing unit at the rate of a clock signal, the central processing unit and at least one of the peripherals each includes a data encryption/decryption cell. Each data encryption/decryption cell uses the same secret key. The secret key is produced locally at each clock cycle in each cell from a random signal synchronous with the clock signal, and is applied to each of the cells by a one-way transmission line.

Abstract: A division method and division circuit that can be integrated into a modular arithmetic coprocessor performs a reversal by word for the dividend and the quotient. This is done using a plurality of registers.

Abstract: A sequential access memory comprises N register elements each storing an information bit. These N register elements are divided into P groups each comprising L elements. In a first phase of operation whose duration corresponds to P-1 consecutive periods of the clock signal, only the last elements of each group are activated and are furthermore series-connected. In a second phase of operation whose duration corresponds to a single period of the clock signal, all the elements are activated simultaneously, the groups of elements being furthermore series-connected. The advantage is that it enables a reduction in the dynamic consumption of the memory.

Abstract: A sequential access memory working at the rate of a clock signal CK includes N register elements N, each storing an information bit. These register elements are divided into L groups, each comprising P elements that are series-connected and simultaneously activated or not activated (with P.times.L=N). The register elements of a given group are activated at least P times consecutively during a part of the time, and are not activated for the rest of the time. Accordingly, each group stores P consecutive information bits each from among the N bits arriving in serial form at the input of the memory. The advantage of the memory is that it enables a reduction in the dynamic energy consumption.