Patents by Inventor Bernard S. Meyerson
Bernard S. Meyerson has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 5159508Abstract: A magnetic head slider having a protective coating on the rails thereof, the protective coating comprising a thin adhesion layer and a thin layer of amorphous hydrogenated carbon. The protective coating is deposited on the air bearing surface of the slider after the thin film magnetic heads are lapped to a chosen dimension, but before the pattern of rails is produced on the air bearing surface. The protective coating protects the magnetic head during the rail fabrication process and in usage in a magnetic recording system protects the magnetic head from wear and corrosion damage.Type: GrantFiled: December 27, 1990Date of Patent: October 27, 1992Assignee: International Business Machines CorporationInventors: Alfred Grill, Cheng T. Horng, Bernard S. Meyerson, Vishnubhai V. Patel, Michael A. Russak
-
Patent number: 5151383Abstract: A method is described for fabricating electroluminescent devices exhibiting visible electroluminescence at room temperature, where the devices include at least one doped layer of amorphous hydrogenated silicon (a-Si:H). The a-Si:H layer is deposited on a substrate by homogeneous chemical vapor deposition (H-CVD) in which the substrate is held at a temperature lower than about 200.degree. C. and the a-Si:H layer is doped in-situ during deposition, the amount of hydrogen incorporated in the deposited layer being 12-50 atomic percent. The bandgap of the a-Si:H layer is between 1.6 and 2.6 eV, and in preferrable embodiments is between 2.0 and 2.6 eV. The conductivity of the a-Si:H layer is chosen in accordance with device requirements, and can be 10.sup.16 -10.sup.19 carriers/cm.sup.2. The bandgap of the a-Si:H layer depends at least in part on the temperature of the substrate on which the layer is deposited, and can be "tuned" by changing the substrate temperature.Type: GrantFiled: February 6, 1989Date of Patent: September 29, 1992Assignee: International Business Machines CorporationInventors: Bernard S. Meyerson, Bruce A. Scott, Donald J. Wolford, Jr.
-
Patent number: 5132765Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.Type: GrantFiled: January 31, 1991Date of Patent: July 21, 1992Inventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg
-
Patent number: 5119157Abstract: A P- semiconductor material substrate which has been ion-implanted with N-type dopants to form an N+ subcollector layer is annealed in Argon to further remove implant damage and drive the dopant ions deeper into the P substrate. Next a lightly doped N- epitaxial layer is grown on the N+ subcollector layer. This forms the blanket collector. A P- well region is formed by growing a pad oxide of 10 nm on the N-epi layer and a 200 nm layer of nitride is then deposited on top of the layer oxide. A photoresist etch mask is used to pattern the P- well region. A reactive ion etch is performed through the dielectric oxide and nitride layers, through the epitaxial layer and stopping in the subcollector layer. A layer of low temperature expitaxial material is grown over the structure using ultra-high vacuum/chemical vapor depositions such that the epitaxial layer extends above the surface of the epitaxial layer and includes a P+ heavily doped layer and a lightly P-doped surface layer.Type: GrantFiled: March 5, 1991Date of Patent: June 2, 1992Assignee: International Business Machines CorporationInventors: David L. Harame, Bernard S. Meyerson, Johannes M. C. Stork
-
Patent number: 5117271Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-aligned elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.Type: GrantFiled: December 7, 1990Date of Patent: May 26, 1992Assignee: International Business Machines CorporationInventors: James H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Yuan-Chen Sun, Denny D. Tang
-
Patent number: 5106767Abstract: This invention relates to a bipolar transistor which incorporates, in a raised base regime, an emitter, collector pedestal and intrinsic and extrinsic bases all of which are self-aligned. The invention also relates to a process for fabricating such devices which obtains the self-alignment of the above mentioned elements using a single lithographic and masking step. The structure of the transistor, in addition to having the self-algined elements, incorporates a composite dielectric isolation layer which not only permits the carrying out of a number of functions during device fabrication but also provides for desired electrical characteristics during device operation. The composite isolation layer consists of an oxide layer adjacent the semiconductor surface; a nitride layer on the oxide layer and an oxide layer on the nitride layer in the final structure of the device.Type: GrantFiled: April 10, 1991Date of Patent: April 21, 1992Assignee: International Business Machines CorporationInventors: Janes H. Comfort, Tze-Chiang Chen, Pong-Fei Lu, Bernard S. Meyerson, Yuan-Chen Sun, Denny D. Tang
-
Patent number: 5057450Abstract: A fabrication method for forming SOI structures where perfect material is grown epitaxially on a substrate and then, through a series of selective etches and oxidations, an insulating layer is formed below the epitaxial silicon. In the method, low temperature epitaxial techniques are employed to grow a layered structure including a first layer p++ silicon on a substrate wafer, a layer of intrinsic silicon is then formed on the first p++ silicon layer, and a second layer of p++ silicon is formed on the intrinsic silicon layer, and a finally a layer of p-silicon is fabricated on top of the second p++ silicon layer. Grooves are formed through the p-layer, the second p++ silicon layer, the intrinsic silicon layer, and stopped in the first p++ silicon layer. An etch is then employed to remove the intrinsic layer long enough for the p++ silicon layer to be totally undercut, leaving an air gap between the two p++ silicon layers.Type: GrantFiled: April 1, 1991Date of Patent: October 15, 1991Assignee: International Business Machines CorporationInventors: Gary B. Bronner, Paul M. Fahey, Bernard S. Meyerson, Wilbur D. Pricer
-
Patent number: 5031029Abstract: A device that contains a copper substrate; a rigidizing layer and/or a metal layer, and a non-graphitic hard carbon layer deposited on the rigidizing layer; and use as a heat sink or piston for electronic components.Type: GrantFiled: April 4, 1990Date of Patent: July 9, 1991Assignee: International Business Machines CorporationInventors: John Acocella, Nanik Bakhru, Alfred Grill, Egidio Marotta, Bernard S. Meyerson, Vishnubhai V. Patel
-
Patent number: 5008207Abstract: There is provided a method for use in the fabrication of a transistor, the method including the steps of: providing a substrate of semiconductor material including a region of first conductivity type; forming a first layer of second conductivity type epitaxial semiconductor material over the region; forming a second layer of second conductivity type epitaxial semiconductor material over the first layer, the second layer of a relatively higher dopant concentration than the first layer; oxidizing a portion of the second layer; and removing the oxidized portion of the second layer to expose a portion of the first layer, the exposed portion of the first layer forming an intrinsic base region. The steps of forming the first and second layers are preferably performed using low temperature, ultra-high vacuum, epitaxial deposition processes.Type: GrantFiled: September 11, 1989Date of Patent: April 16, 1991Assignee: International Business Machines CorporationInventors: Jeffrey L. Blouse, Inge G. Fulton, Russell C. Lange, Bernard S. Meyerson, Karen A. Nummy, Martin Revitz, Robert Rosenberg
-
Patent number: 4972246Abstract: A homojunction bipolar transistor having a superlattice base region comprising alternate layers of extrinsic and intrinsic layers, with extrinsic layers being of the opposite conductivity of the emitter and collector layers of the transistor. The alternate extrinsic and intrinsic layers have substantially different doping levels providing abrupt transitions in the valence and conduction bands between layers. The abrupt transitions result in the energy band gap in the base region being effectively reduced with respect to the band gap in the emitter region. In one embodiment, the effective narrow band gap base transistor is implemented by converting a portion of the upper layers of the superlattice to a homogeneous region by heavily doping the portion to form the emitter of the transistor.Type: GrantFiled: March 22, 1988Date of Patent: November 20, 1990Assignee: International Business Machines Corp.Inventors: Marc H. Brodsky, Frank F. Fang, Bernard S. Meyerson
-
Patent number: 4684542Abstract: A process for preparing tungsten silicide films using low pressure, low temperature chemical vapor deposition to deposit silicon-rich tungsten silicide films. As a source of silicon, higher order silanes, such as disilane and trisilane, are used. The gaseous tungsten source is WF.sub.6. The substrate temperature range is less than about 370.degree. C., while the total pressure range is in the range 0.05-1 Torr. WF.sub.6 flow rates are generally less than 25 sccm, while the higher order silane flow rates are generally less than about 400 sccm.Type: GrantFiled: August 11, 1986Date of Patent: August 4, 1987Assignee: International Business Machines CorporationInventors: Joseph M. Jasinski, Bernard S. Meyerson, Bruce A. Scott
-
Patent number: 4647494Abstract: A superior wear-resistant coating is provided for metallic magnetic recording layers, where the improved coating is a hard carbon layer that is strongly bound to the underlying metallic magnetic recording layer by an intermediate layer of silicon. The silicon layer can be very thin, with a minimum thickness of a few atomic layers, and provides strong adhesion between the hard carbon protective layer and the metallic magnetic recording layer. A preferred technique for depositing both the intermediate silicon layer and the hard carbon layer is plasma deposition, since both of these depositions can be performed in the same reactor without breaking vacuum.Type: GrantFiled: October 31, 1985Date of Patent: March 3, 1987Assignee: International Business Machines CorporationInventors: Bernard S. Meyerson, Rajiv V. Joshi, Robert Rosenberg, Vishnubhai V. Patel
-
Patent number: 4592933Abstract: A technique and apparatus for homogeneous chemical vapor deposition (HCVD), wherein a heated carrier gas is mixed with a source gas in a location close to a substrate on which deposition is to occur. The heated carrier gas transfers heat to the source gas in order to decompose it, producing the intermediate species necessary for deposition onto the substrate. Thus, the source gas is not subjected to heating above its pyrolysis temperature prior to being transported to the immediate vicinity of the substrate. This HCVD apparatus includes a heat source for heating the carrier gas, a tube for bringing the heated carrier gas to a location close to the substrate, and another tube for bringing the reactive source gas to the aforementioned location where it is mixed with the hot carrier gas to cause decomposition of the source gas close to the substrate. The substrate temperature is decoupled from the hot gas temperature and is significantly colder than the hot gas temperature.Type: GrantFiled: June 29, 1984Date of Patent: June 3, 1986Assignee: International Business Machines CorporationInventors: Bernard S. Meyerson, Richard M. Plecenik, Bruce A. Scott
-
Patent number: 4526593Abstract: A flow control device for filtering and restricting the flow of gas from a gas supply system. Gases stored under pressure in containers or tanks are widely employed in many industries. Such gases are often toxic or explosive, and systems employing such gases must be secure against leaks, clogging and the like. The connector fitting structure includes a flow restrictor plug device and a filter. The connector fitting includes screw threads and may be easily screwed into an end fitting of a gas container and which requires no additional joints to be added to the gas system wherein a minimum volume of gas is trapped external to the gas container in the event of a clogging condition.Type: GrantFiled: April 4, 1983Date of Patent: July 2, 1985Assignee: International Business Machines CorporationInventor: Bernard S. Meyerson
-
Patent number: 4504331Abstract: In intermetallic semiconductor crystal growth such as the growth of GaAs and GaAlAs, silicon as a dopant can be introduced more efficiently and evenly when provided as a gaseous hydride based compound involving a molecule where there are joined silicon atoms such as Si.sub.2 H.sub.6 to Si.sub.5 H.sub.12.Type: GrantFiled: December 8, 1983Date of Patent: March 12, 1985Assignee: International Business Machines CorporationInventors: Thomas F. Kuech, Bernard S. Meyerson
-
Patent number: 4436797Abstract: An improved X-ray lithography mask has been fabricated by forming an X-ray absorbing lithography pattern on a supporting foil of hydrogenated amorphous carbon. The substrate foil is formed by depositing a carbon film in the presence of hydrogen onto a surface having a temperature below 375.degree. C. The hydrogen concentration is maintained sufficiently high that the resulting film has at least one atom percent of hydrogen. A film having about 20 atom percent of hydrogen is preferred. While impurities are permitted, impurities must be maintained at a level such that the optical bandgap of the resulting film is at least one electron volt. A film with an optical bandgap of about 2 electron volts is preferred.Type: GrantFiled: June 30, 1982Date of Patent: March 13, 1984Assignee: International Business Machines CorporationInventors: Michael J. Brady, Bernard S. Meyerson, John M. Warlaumont