Patents by Inventor Bernard Sell

Bernard Sell has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9923054
    Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
    Type: Grant
    Filed: May 29, 2015
    Date of Patent: March 20, 2018
    Assignee: Intel Corporation
    Inventors: Ritesh Jhaveri, Bernard Sell, Tahir Ghani
  • Publication number: 20150287779
    Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
    Type: Application
    Filed: May 29, 2015
    Publication date: October 8, 2015
    Inventors: Ritesh Jhaveri, Bernard SELL, Tahir GHANI
  • Patent number: 9048260
    Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
    Type: Grant
    Filed: December 31, 2011
    Date of Patent: June 2, 2015
    Assignee: Intel Corporation
    Inventors: Ritesh Jhaveri, Bernard Sell, Tahir Ghani
  • Publication number: 20140191300
    Abstract: A hard mask etch stop is formed on the top surface of tall fins to preserve the fin height and protect the top surface of the fin from damage during etching steps of the transistor fabrication process. In an embodiment, the hard mask etch stop is formed using a dual hard mask system, wherein a hard mask etch stop layer is formed over the surface of a substrate, and a second hard mask layer is used to pattern a fin with a hard mask etch stop layer on the top surface of the fin. The second hard mask layer is removed, while the hard mask etch stop layer remains to protect the top surface of the fin during subsequent fabrication steps.
    Type: Application
    Filed: December 31, 2011
    Publication date: July 10, 2014
    Inventors: Ritesh Jhaveri, Bernard Sell, Tahir Ghani