Patents by Inventor Bernard T. Murphy

Bernard T. Murphy has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4639615
    Abstract: An integrated circuit chip in which clock pulses are distributed to a plurality of circuits includes a pattern of trimmable elements such as capacitors or transistors. The capacitors or transistors are trimmed during manufacture in order, for example, to adjust clock skew.
    Type: Grant
    Filed: December 28, 1983
    Date of Patent: January 27, 1987
    Assignee: AT&T Bell Laboratories
    Inventors: Charles M. Lee, Bernard T. Murphy
  • Patent number: 4586073
    Abstract: A high voltage solid-state switch, which provides bidirectional blocking, consists of a first p- type semiconductor body on an n type semiconductor substrate. A p+ type anode region and an n+ type cathode region exist in portions of the semiconductor body. A second p type region of higher impurity concentration than the semiconductor body surrounds the cathode region. The anode region and second p type region are separated from each other by a portion of the semiconductor body. The semiconductor substrate, which acts as a gate, has an electrode connected thereto. Separate electrodes are connected to the anode and cathode regions.
    Type: Grant
    Filed: March 27, 1981
    Date of Patent: April 29, 1986
    Assignee: AT&T Bell Laboratories
    Inventors: Adrian R. Hartman, Bernard T. Murphy, Terence J. Riley, Peter W. Shackle
  • Patent number: 4140558
    Abstract: Disclosed is a method of isolating portions of integrated circuits which permits closely packed structures. A semiconductor wafer is provided with a substrate of one conductivity type, a first layer of opposite conductivity type and high impurity concentration formed thereon, and a second layer of either conductivity type but lower concentration formed over the first layer. The major surfaces of the semiconductor layers are parallel to the (110) plane. Narrow grooves with sidewalls in the (111) plane are etched into the first layer. A shallow diffusion of impurities of the same conductivity type as the first layer is performed in the sidewalls and bottom of the grooves which permits the first layer to be contacted from the surface of the second layer. The groove is then etched further until it extends into the underlying substrate. Impurities of the same conductivity type as the substrate are diffused into the bottom and sidewalls of the grooves.
    Type: Grant
    Filed: March 2, 1978
    Date of Patent: February 20, 1979
    Assignee: Bell Telephone Laboratories, Incorporated
    Inventors: Bernard T. Murphy, James C. North