Abstract: The present invention provides a solid state illuminating system having a centralized controlling module, coupled with a monitoring module and a power supplying module, for converting electricity from a second format to a third format so as to embed a PWM signal therein in accordance with a status signal obtained by an user via a monitoring module. Accordingly, the present invention is capable of supporting various kinds of potential dimming control method and has the advantage of low manufacturing cost without substantially adjustment to the present illumining system.

Abstract: The present invention provides a solid state illuminating system having a centralized controlling module, coupled with a monitoring module and a power supplying module, for converting electricity from a second format to a third format so as to embed a PWM signal therein in accordance with a status signal obtained by an user via a monitoring module. Accordingly, the present invention is capable of supporting various kinds of potential dimming control method and has the advantage of low manufacturing cost without substantially adjustment to the present illumining system.

Abstract: A system includes a processor, a voltage regulator and a circuit. The processor uses a first supply voltage to furnish a first indication of a second supply voltage to be received by the processor. The voltage regulator furnishes the second supply voltage in response to both the first indication and a second indication that the first supply voltage is valid. The circuit provides the second indication and regulates a timing of the second indication to prevent the voltage regulator from furnishing the second supply voltage until a predefined interval of time has elapsed after the first supply voltage becomes valid.

Abstract: A method includes converting a first voltage into a second voltage. The second voltage is routed to a power supply line when the second voltage exceeds a first predefined threshold, and the second voltage is isolated from the power supply line when the first voltage decreases below a second predefined voltage.

Abstract: A system includes a processor, a voltage regulator and a circuit. The processor uses a first supply voltage to furnish a first indication of a second supply voltage to be received by the processor. The voltage regulator furnishes the second supply voltage in response to both the first indication and a second indication that the first supply voltage is valid. The circuit provides the second indication and regulates a timing of the second indication to prevent the voltage regulator from furnishing the second supply voltage until a predefined interval of time has elapsed after the first supply voltage becomes valid.

Abstract: A system includes a first power supply line that is associated with a first voltage level and a second power supply line that is associated with a second voltage level. A power supply is coupled to the first and second power lines to establish a first voltage of the first power supply line near the first voltage level and a second voltage of the second power supply line near the second voltage level. The power supply has a response during a time period after the activation or deactivation of the power supply in which the power supply does not maintain a difference between the first and second voltages within a predefined range. The system includes a circuit that is coupled to the first and second power supply lines to maintain the difference between the first and second voltages within the predefined range during the time period.

Abstract: A technique for improving the frequency response of a semiconductor device employing silicon as the semiconductor material. Parasitic components inherent in semiconductor devices degrade the performance of these devices at higher frequencies. Typically, a parasitic capacitor includes a dielectric material sandwiched between a conductive interconnect (31A, 31B) and a substrate (10) or a bottom contact (18). Further, in the past, the thickness of this dielectric material has been similar to that of the third dielectric material (17) of the present invention. However, in the present invention the effective thickness of the dielectric material has been increased by including a first and second dielectric material (15, 16) as well as the third dielectric material (17). Increasing the thickness of the dielectric of a parasitic capacitor decreases the value of the parasitic capacitance; and therefore increases the cut-off frequency of the semiconductor device.

Abstract: The reverse breakdown voltage of a conventional insulated gate transistor is greatly increased by the addition of a lightly doped layer between the substrate and a buffer layer of the insulated gate transistor. The addition of the lightly doped layer does not increase the on resistance of the device, nor the cut-off time of the device. The lightly doped layer can be provided as an epitaxial layer along with the other epitaxial layers of the insulated gate transistor.

Abstract: An improved high frequency dielectrically isolated (DIC) transistor (100) or integrated circuit is obtained by providing a highly doped single crystal semiconductor region (112) coupled to the device reference terminal (16') and extending between front (98) and rear (61) faces of the semiconductor die. This allows the reference terminal (16', 116) to be coupled to the package ground plane without use of wire bonds, thereby lowering the common mode impedance. The desired structure is formed in connection with DIC devices (100) by etching first (66) and second (77) nested cavities into a single crystal substrate (60). The cavities (66) form protruding islands (821, 822) of single crystal semiconductor having a height (80+68) about equal the final die thickness (110) and which, after conventional DIC processing using an oxide isolation layer (86) and a poly handle (88), are exposed by grinding away the poly handle (88) to expose the highly doped, single crystal reference terminal feed-through (112).

Abstract: A substantially planar dielectric wafer is formed by utilizing a polysilicon filler to remove surface irregularities (15, 15'). The polysilicon filler is formed by filling surface irregularities (15, 15') with polysilicon (19) and polishing the polysilicon (19) to form a substantially planar surface. A polishing stop (18) terminates the polishing and prevents damage to the wafer's isolated tubs (13). The polishing stop (18) can also be used as a mask during field oxide growth. The polysilicon filler also protects underlying areas (12) from subsequent etch operations. During subsequent field oxide growth, polysilicon layer (19) is converted to silicon dioxide which enhances dielectric isolation of each tub (13).

Abstract: A method is described for planarizing isolated regions (12) and active regions (22) of a semiconductor wafer (10). Semiconductor wafer (10) is provided with islands of dielectric (12) that cover portions of the semiconductor wafer (10), while leaving other portions of the semiconductor wafer (10) exposed. The dielectric islands (12) have a polysilicon layer (13) that covers the dielectric islands' (12) top surface. A blanket layer of silicon is deposited on the polysilicon layer (13) that covers the top surface of the dielectric islands and is deposited between the dielectric islands (12). Planarizing the blanket layer of epitaxial silicon is achieved by a chemical-mechanical means, thereby producing a planar surface of isolated areas (12) and active areas (22).

Abstract: Integrated high voltage transistors having minimum transistor to transistor crosstalk are fabricated in refilled epitaxial tubs, which are formed in a heavily doped substrate. The heavily doped substrate provides the isolation between each transistor, and thus provides for minimum transistor to transistor crosstalk. The voltage capability of the transistor is increased by forming the base surrounding the collector contact in the refilled epitaxial tub.

Abstract: Improved dielectrically isolated semiconductor structures especially suited for very high frequency bipolar transistors are produced. Recesses are formed in a (e.g., N.sup.+) single crystal semiconductor wafer, the wafer surface is coated with a dielectric, and a thick polycrystalline semiconductor layer is deposited thereon to provide a support. The single crystal wafer is back-lapped to expose dielectrically isolated N.sup.+ islands located between the original recesses. Depressions are etched in the N.sup.+ islands and the exposed surface is covered by a more lightly doped (e.g., N.sup.-) semiconductor layer which is, generally, single crystal above the N.sup.+ islands and non-single crystal therebetween, and which at least fills the depressions. The structure is then planarized (e.g., by lapping and etching) to remove this non-single crystal material and give isolated single crystal islands having a surrounding N.sup.+ periphery and an N.sup.

Abstract: An improved monolithic, temperature compensated voltage- reference diode is realized by creating a tub of epitaxial semiconductor material in a substrate of opposite conductivity type and creating a voltage reference junction at a surface of the tub. The junction between the tub and the substrate forms the forward-biased, temperature compensating junction of the device. The dopant concentration is varied during growth of the epitaxial material to provide a relatively low resistivity at the voltage-reference junction and a higher resistivity at the temperature compensating junction. The method described offers significant improvement over prior methods of manufacturing such devices in the area of cost and reliability.

Abstract: An improved monolithic, temperature compensated voltage-reference diode is realized by creating a tub of epitaxial semiconductor material in a substrate of opposite conductivity type and creating a voltage reference junction at a surface of the tub. The junction between the tub and the substrate forms the forward-biased, temperature compensating junction of the device. The dopant concentration is varied during growth of the epitaxial material to provide a relatively low resistivity at the voltage-reference junction and a higher resistivity at the temperature compensating junction. The method described offers significant improvement over prior methods of manufacturing such devices in the area of cost and reliability.

Abstract: A process is disclosed for controllably providing dielectrically isolated semiconductor regions having a uniform and well defined thickness. Grooves are formed in a first surface of a semiconductor substrate and then a dielectric layer is formed covering that surface and the grooves extending into the surface. A layer of backing material such as polycrystalline silicon is formed overlying the dielectric layer. A semiconductor substrate is then thinned to form a new surface with portions of the dielectric layer and backing material exposed at that surface. A semiconductor layer is epitaxially grown overlying the new surface with the semiconductor layer having a monocrystalline structure where it is grown on exposed regions of the original substrate and having a polycrystalline structure otherwise. An oxidation masking layer is formed overlying those portions of the semiconductor layer which have a monocrystalline structure.

Abstract: A process is disclosed for manufacturing electrically isolated semiconductor device structures. The process includes the steps of providing a semiconductor substrate and selectively etching one surface of that substrate to form etched regions and unetched regions. In a single epitaxial growth step three separate epitaxial layers are grown overlying both the etched and unetched regions. The epitaxial layers are then shaped back to form a substantially planar surface and to expose portions of the first epitaxial layer. The exposed portion of the first epitaxial layer, in combination with the substrate, is suitable for the fabrication of a back contact power transistor. The second epitaxial layer, which follows the contour of the etched surface, bends upwardly and intersects the planar surface to substantially surround portions of the third epitaxial layer and to electrically isolate those portions of the third epitaxial layer from the substrate and first epitaxial layer.

Abstract: An improved means and method is provided for forming isolated device regions suitable for the construction of control circuits and devices, in the presence of and isolated from other device regions suitable for the construction of bottom-contact power devices. In a preferred embodiment the desired structure is obtained by growing a first epitaxial layer on a semiconductor substrate, providing a patterned mask in which areas of the epitaxial layer are exposed to be etched, etching recesses in the exposed areas to a first depth to leave pedestals beneath the masked areas, and forming a second and third epitaxial layer on the substrate to fill the recesses. The second epitaxial layer is U-shaped and conformally coats the bottom and sides of the recesses. The U-shaped layer acts as the isolation layer separating the first epitaxial layer portions in the pedestals wherein the power devices will be built, from the third epitaxial layer regions which fill in the U, where the control devices will be built.

Abstract: An insulated gate field-effect transistor is fabricated to include an improved insulation layer comprising a film of silicon dioxide covered with a film of silicon nitride. The method of fabrication includes the thermal oxidation of a semiconductor silicon surface in a "reducing" atmosphere. The use of hydrogen as a carrier gas for oxygen provides a thermally grown, pinhole-free oxide film having improved stability under conditions of heat cycling and electrical bias. The process permits a control of oxidation rate by adjusting the oxygen content of the gaseous mixture, rather than by the control of temperature. Best device characteristics are obtained by proceeding immediately with the vapor deposition of silicon nitride on the oxide, as a substantially continuous operation in the same reactor.