Abstract: A new method to produce a contact or via opening and filled metallurgy for integrated circuits. An insulating layer structure is formed over semiconductor device structures. A resist mask with substantially vertical sided openings is formed in the mask over the insulating layer and above the device elements to be electrically contacted. These device elements can be, for example source/drain regions in the semiconductor substrate, a metallurgy layer interconnecting other device element and the like. The exposed insulating layer is isotropically etched to a depth of between about 500 to 850 Angstroms to form a break in the vertical sided opening under construction. The exposed insulating layer is anisotropically etched to complete the construction of the substantially vertical sided openings through the insulating layer to a device element to be electrically contacted.

Abstract: The method of manufacture of a PMOS integrated circuit having a feature size in the order of one micron or less is done by providing, on a silicon substrate, a pattern of silicon gate electrodes over a gate dielectric. Implanting of BF.sub.2 + ions and B11+ ions sequentially by using the pattern as a mask. The structure is annealed at more than about 850.degree. C. to complete the PMOS integrated circuit. This method results in lower contact resistance to the P+ regions and lower sheet resistance for higher speed CMOS integrated circuits at minimal increase of manufacturing cost.

Abstract: A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.

Abstract: A three-layer metal contact including aluminum is provided for silicon-based semiconductor devices to minimize the effects of formation of silicon precipitates in the aluminum layer and low contact junction leakage. The metal contact comprises a first layer of a refractory metal silicide formed on a silicon surface, an intermediate layer of aluminum formed on the refractory metal silicide and a top layer of a refractory metal silicide formed on the layer of aluminum. Where contact is made to polysilicon layers forming high resistance load resistors, the metal contact of the invention prevents reduction in resistance resulting from the interdiffusion of silicon and aluminum.