Patents by Inventor BERNARDETTE KUNERT

BERNARDETTE KUNERT has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11004962
    Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.
    Type: Grant
    Filed: August 27, 2019
    Date of Patent: May 11, 2021
    Assignee: IMEC vzw
    Inventors: Robert Langer, Niamh Waldron, Bernardette Kunert
  • Publication number: 20210111021
    Abstract: The present invent provides a method comprising forming a first wafer comprising a first substrate of a group IV semiconductor, and a group III-V semiconductor device structure formed by selective area epitaxial growth on a surface portion of a front side of the first substrate. The method further comprises forming a second wafer comprising a second substrate of a group IV semiconductor, and a group IV semiconductor device structure formed on a front side of the second substrate, and bonding the first wafer to the second wafer with the front side of the first substrate facing the front side of the second wafer.
    Type: Application
    Filed: October 12, 2020
    Publication date: April 15, 2021
    Inventors: Philippe SOUSSAN, Vasyl MOTSNYI, Luc HASPESLAGH, Stefano GUERRIERI, Olga SYSHCHYK, Bernardette KUNERT, Robert LANGER
  • Publication number: 20210062360
    Abstract: A method for growing at least one III/V nano-ridge on a silicon substrate in an epitaxial growth chamber. The method comprises: patterning an area on a silicon substrate thereby forming a trench on the silicon substrate; growing the III/V nano-ridge by initiating growth of the III/V nano-ridge in the trench, thereby forming and filling layer of the nano-ridge inside the trench, and by continuing growth out of the trench on top of the filling layer, thereby forming a top part of the nano-ridge, wherein at least one surfactant is added in the chamber when the nano-ridge is growing out of the trench.
    Type: Application
    Filed: August 18, 2020
    Publication date: March 4, 2021
    Inventors: Bernardette Kunert, Robert Langer, Yves Mols, Marina Baryshnikova
  • Publication number: 20200203930
    Abstract: The disclosed technology relates to the development of a monolithic active electro-optical device. In some embodiments, the electro-optical device may be fabricated using the so-called nanoridge aspect ratio trapping (ART) approach. In one aspect, the electro-optical device is a monolithic integrated electro-optical device comprising a first-conductivity-type Si-based support region and a III-V-semiconductor-material ridge structure extending from the Si-based support region, wherein the ridge structure contains a recombination region. Furthermore, the device comprises a III-V-semiconductor capping layer having a higher band-gap than that of the III-V semiconductor material of the ridge structure and being formed on an outer surface of the ridge structure.
    Type: Application
    Filed: December 18, 2019
    Publication date: June 25, 2020
    Inventors: Yannick De Koninck, Bernardette Kunert, Joris Van Campenhout, Maria Ioanna Pantouvaki, Nadezda Kuznetsova
  • Patent number: 10690852
    Abstract: A III-V semiconductor waveguide nanoridge structure having a narrow supporting base with a freestanding wider body portion on top, is disclosed. In one aspect, the III-V waveguide includes a PIN diode. The waveguide comprises a III-V semiconductor waveguide core formed in the freestanding wider body portion; at least one heterojunction incorporated in the III-V semiconductor waveguide core; a bottom doped region of a first polarity positioned at a bottom of the narrow supporting base, forming a lower contact; and an upper doped region of a second polarity, forming an upper contact. The upper contact is positioned in at least one side wall of the freestanding wider body portion.
    Type: Grant
    Filed: December 20, 2018
    Date of Patent: June 23, 2020
    Assignees: IMEC vzw, Universiteit Gent
    Inventors: Joris Van Campenhout, Ashwyn Srinivasan, Bernardette Kunert, Maria Ioanna Pantouvaki
  • Patent number: 10678007
    Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.
    Type: Grant
    Filed: October 3, 2018
    Date of Patent: June 9, 2020
    Assignees: IMEC VZW, Universiteit Gent
    Inventors: Joris Van Campenhout, Bernardette Kunert, Maria Ioanna Pantouvaki, Dries Van Thourhout, Yuting Shi
  • Publication number: 20200091003
    Abstract: A method for forming a semiconductor structure comprising: providing a silicon substrate having a first and a second flat top surface belonging to a first and a second substrate region respectively, the first top surface being lower than the second top surface, thereby forming a step delimiting the first and the second substrate region. The method further comprises forming, at least partially, one or more silicon semiconductor devices in the second substrate region, and forming, at least partially, one or more III-V semiconductor devices in the first substrate region.
    Type: Application
    Filed: August 23, 2019
    Publication date: March 19, 2020
    Inventors: Amey Mahadev Walke, Liesbeth Witters, Niamh Waldron, Robert Langer, Bernardette Kunert
  • Publication number: 20200075750
    Abstract: The disclosed technology generally relates to integrated circuit devices having at least one transistor, and methods of fabricating the same. In one aspect, an integrated circuit device can be produced from a silicon substrate and can include at least one nano-ridge transistor formed from III-V semiconducting crystal portions. The III-V portions can be grown epitaxially from the silicon substrate using an intermediate portion which can be adapted to produce aspect ratio trapping. The nano-ridge transistor can have a reduced footprint on the silicon substrate, may be adapted for power RF applications, and can be combined with MOS or CMOS transistors within one and a same integrated circuit.
    Type: Application
    Filed: August 27, 2019
    Publication date: March 5, 2020
    Inventors: Robert Langer, Niamh Waldron, Bernardette Kunert
  • Patent number: 10566250
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.
    Type: Grant
    Filed: February 8, 2019
    Date of Patent: February 18, 2020
    Assignee: IMEC vzw
    Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
  • Publication number: 20190244862
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.
    Type: Application
    Filed: February 8, 2019
    Publication date: August 8, 2019
    Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
  • Publication number: 20190219846
    Abstract: A III-V semiconductor waveguide nanoridge structure having a narrow supporting base with a freestanding wider body portion on top, is disclosed. In one aspect, the III-V waveguide includes a PIN diode. The waveguide comprises a III-V semiconductor waveguide core formed in the freestanding wider body portion; at least one heterojunction incorporated in the III-V semiconductor waveguide core; a bottom doped region of a first polarity positioned at a bottom of the narrow supporting base, forming a lower contact; and an upper doped region of a second polarity, forming an upper contact. The upper contact is positioned in at least one side wall of the freestanding wider body portion.
    Type: Application
    Filed: December 20, 2018
    Publication date: July 18, 2019
    Inventors: Joris Van Campenhout, Ashwyn Srinivasan, Bernardette Kunert, Maria loanna Pantouvaki
  • Patent number: 10340188
    Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.
    Type: Grant
    Filed: August 25, 2017
    Date of Patent: July 2, 2019
    Assignee: IMEC vzw
    Inventors: Yves Mols, Niamh Waldron, Bernardette Kunert
  • Publication number: 20190101711
    Abstract: Example embodiments relate to active-passive waveguide photonic systems. An example embodiment includes a monolithic integrated active/passive waveguide photonic system. The system includes a substrate having positioned thereon at least one active waveguide and at least one passive waveguide. The at least one active waveguide and the at least one passive waveguide are monolithically integrated and are arranged for evanescent wave coupling between the waveguides. The at least one active waveguide and the at least one passive waveguide are positioned so that at least a portion of each waveguide does not overlap the other waveguide, both in a height direction and in a lateral direction with respect to the substrate.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 4, 2019
    Applicants: IMEC VZW, Universiteit Gent
    Inventors: Joris Van Campenhout, Bernardette Kunert, Maria Ioanna Pantouvaki, Dries Van Thourhout, Shi Yuting
  • Patent number: 10224250
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: March 5, 2019
    Assignee: IMEC vzw
    Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
  • Publication number: 20180082901
    Abstract: The disclosed technology generally relates to semiconductor devices, and more specifically to a semiconductor device having a high aspect ratio channel layer. In one aspect, semiconductor device includes a semiconductor substrate having formed thereon a dielectric isolation layer having an opening formed therethrough. The semiconductor device additionally includes a filling isolation structure having a portion formed in the opening and a portion protruding above the dielectric isolation layer, wherein the filling isolation structure comprises a dielectric filling layer. The semiconductor device additionally includes a dielectric layer formed on the dielectric isolation layer, wherein the dielectric layer and the dielectric filling layer have top surfaces that are substantially co-planar to form a common top surface.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 22, 2018
    Inventors: Bernardette Kunert, Niamh Waldron, Weiming Guo
  • Publication number: 20180061712
    Abstract: The disclosed technology generally relates to manufacturing of semiconductor devices, and more particularly to manufacturing of a semiconductor device by transferring an active layer from a donor substrate. One aspect is a method of manufacturing a semiconductor device includes providing a donor wafer for transferring an active layer, comprising a group IV, a group III-IV or a group II-VI semiconductor material, to a handling wafer. The method includes forming the active layer on a sacrificial layer of the donor wafer, bonding the donor wafer to the handling wafer, and selectively etching the sacrificial layer to remove the donor wafer from the handling wafer, thereby leaving the active layer on the handling wafer.
    Type: Application
    Filed: August 25, 2017
    Publication date: March 1, 2018
    Inventors: Yves Mols, Niamh Waldron, Bernardette Kunert
  • Patent number: 9876080
    Abstract: Disclosed herein is a semiconductor structure including: (i) a monocrystalline substrate having a top surface, (ii) a non-crystalline structure overlying the monocrystalline substrate and including an opening having a width smaller than 10 microns and exposing part of the top surface of the monocrystalline substrate. The semiconductor structure also includes (iii) a buffer structure having a bottom surface abutting the part and a top surface having less than 108 threading dislocations per cm2, the buffer structure being made of a material having a first lattice constant. The semiconductor structure also includes (iv) one or more group IV monocrystalline structures abutting the buffer structure and that are made of a material having a second lattice constant, different from the first lattice constant.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: January 23, 2018
    Assignee: IMEC VZW
    Inventors: Bernardette Kunert, Robert Langer, Geert Eneman
  • Patent number: 9865689
    Abstract: A monolithic integrated semiconductor structure includes: A) an Si carrier layer, B) a layer having the composition BxAlyGazNtPv, wherein x=0-0.1, y=0-1, z=0-1, t=0-0.1 and v=0.9-1, C) a relaxation layer having the composition BxAlyGazInuPvSbw, wherein x=0-0.1, y=0-1, z=0-1, u=0-1, v=0-1 and w=0-1, wherein w and/or u is on the side facing toward layer A) or B) smaller than, equal to, or bigger than on the side facing away from layer A) or B) and wherein v=1?w and/or y=1?u?x?z, and D) a group III/V, semiconductor material. The sum of the above stoichiometric indices for all group III elements and for all group V elements are each equal to one.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: January 9, 2018
    Assignee: NASP III/V GMBH
    Inventor: Bernardette Kunert
  • Patent number: 9614082
    Abstract: The present disclosure relates to a semiconductor structure and a method of preparation including a silicon monocrystalline substrate, and a III-V structure abutting the silicon monocrystalline substrate. The semiconductor structure includes an InaGabAs structure overlaying the III-V structure, where a is from 0.40 to 1, b from 0 to 0.60, and a+b equal to 1.00. The III-V structure has a top surface facing away from the silicon substrate. The top surface is GagXxPpSbsZz, where X includes one or more group III elements other than Ga and Z is one or more group V elements other than P or Sb. g is from 0.80 to 1.00, x is from 0 to 0.20, z is from 0 to 0.30, p is from 0.10 to 0.55, and s is from 0.50 to 0.80, g+x is equal to 1.00 and p+s+z is equal to 1.00.
    Type: Grant
    Filed: July 13, 2016
    Date of Patent: April 4, 2017
    Assignee: IMEC VZW
    Inventors: Bernardette Kunert, Robert Langer
  • Patent number: 9595438
    Abstract: A method for producing a monolithic template comprises a Si wafer with a layer of a III/V semiconductor epitaxially applied to its surface. The III/V semiconductor has a lattice constant differing by less than 10% from that of Si. The method includes epitaxially growing a layer of a III/V semiconductor on the surface of the Si wafer at a wafer temperature from 350 to 650° C., a growth rate from 0.1 to 2 ?m/h, and a layer thickness from 1 to 100 nm. A layer of another III/V semiconductor, identical to or different from the previously applied III/V semiconductor, is epitaxially grown on the III/V semiconductor layer at a wafer temperature from 500 to 800° C., a growth rate from 0.1 to 10 ?m/h, and a layer thickness from 10 to 150 nm.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: March 14, 2017
    Assignee: NASP III/V GMBH
    Inventor: Bernardette Kunert