Abstract: A data processing device has a configurable functional unit for executing an instruction according to a configurable function. The configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to implement the configurable function. Configurable connection circuits are provided between the configurable logic blocks and both the inputs and the outputs of the configurable functional unit. This allows an optimalization of the distribution of logic functions over the configurable logic blocks.

Abstract: A processing system according to the invention comprises a plurality of processing elements (PE1, . . . , PE7). The processing elements comprise a controller and computation means. The plurality of processing elements is dynamically reconfigurable as mutually independently operating task units (TU1, TU2, TU3), which task units comprise one processing element (PE7) or a cluster of two or more processing elements (PE3, PE4, PE5, PE6). The processing elements within a cluster are arranged to execute instructions under a common thread of program control. In this way the processing system is capable of using the same sub-set of data-path elements to exploit instruction level parallelism or task level parallelism or a combination thereof, dependent on the application.

Abstract: A method is disclosed for partitioning a specification in a source code. In a first step, the specification is converted into a plurality of abstract syntax trees. In a second step, the plurality of abstract syntax trees is partitioned into at least a first set and a second set. The first set of abstract syntax trees is to be implemented by a first processor and the second set of abstract syntax trees is to be implemented by a second processor. The first and second set of abstracts syntax trees are translated to a specification in the original source code language, respectively, allowing the user to add manual changes to the specifications. Furthermore, specific compiler and design tools are used to convert the specifications into corresponding executable machine code and a specification of the co-processor.

Abstract: A processor comprises a main controller (CTR11) and a plurality of processing units (1–9). Each processing unit (1–9) has a local controller (CTR1–CTR9) and at least one functional unit (FU1–FU9) controllable by the local controller (CTR1–CTR9). The local controller (CTR1–CTR9) of a processing unit (1–9) is coupled (15) to the main controller (CTR11). The processor further comprises an instruction set, having at least one instruction for increasing the activity of at least one processing unit (1–9). The main controller (CTR11) is arranged to process the at least one instruction for increasing the activity of at least one processing unit (1–9). One or more processing units (1–9) of the processor can be completely switched off, including the corresponding local controller (CTR1–CTR9), since the instructions for switching on a processing unit (1–9) are not processed by the corresponding local controller (CTR1–CTR9), but by the main controller (CTR11) itself.

Abstract: The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for processing said input data based on control signals generated from instruction data, wherein the depth of the register means (DCF) is controlled in accordance with the instruction data. Thereby, systolic arrays can be mapped onto a programmable processor, e.g. a VLIW processor, without the need for explicitly issuing operations to implement the register moves that constitute the delay lines of the array.

Abstract: A processing system according to the invention comprises a plurality of processing elements, and the plurality of processing elements comprises a first set of processing elements and at least a second set of processing elements. Each processing element of the first set comprises a register file and at least one instruction issue slot, and the instruction issue slot comprises at least one functional unit. This type of processing element is dedicated for executing a thread with no or a very low degree of instruction-level parallelism. Each processing element of the second set comprises a register file and a plurality of instruction issue slots, and each instruction issue slot comprising at least one functional unit. This type of processing element is dedicated for executing a thread with a large degree of instruction-level parallelism. All processing elements are arranged to execute instructions under a common thread of control.

Abstract: The present invention relates to a method and apparatus for decoding a sequence of at least two instructions of a data processing program into a sequence of code words used to control a data path, wherein an invariant code word portion which does not change in said sequence of code words is separately generated and used to configure a part of the data path to be fixed during the sequence of code words. Thereby, the necessary micro code memory size can be reduced and power consumption can be decreased.

Abstract: A design method for designing an integrated circuit (IC) and a corresponding integrated circuit design tool are presented. An IC design having a plurality of building blocks (121-129) being interconnected by a plurality of interconnection wires (131-139) is represented by a two-dimensional representation (200) mimicking the positions of the building blocks (121-129) and interconnections (131-139) in the actual IC lay-out. The two-dimensional representation allows the IC designer to evaluate the lengths of the interconnection wires (131-139), which enables the IC designer to alter the IC design before the IC design back-end, e.g. the IC area optimization, is entered, thus leading to a more effective IC design method.

Abstract: Target systems combining a number of different processors, for example a general-purpose processor (GP) and at least one co-processor (COP), or alternatively two or more co-processors (COPA, COPB, COPC), allow combining flexibility and speed for execution of a set of functions. The design of such target systems requires partitioning of a specification in a part to be implemented by the general-purpose processor and a part to be implemented by a co-processor, or into several parts to be implemented by different co-processors. The present invention describes a method for partitioning a specification in a source code. In a first step, the specification 301 is converted into a plurality of abstract syntax trees 101. In a second step, the plurality of abstract syntax trees 101 is partitioned into at least a first set 201 and a second set 203.

Abstract: The present invention describes an integrated circuit (100) having a processor that consists of a plurality of identical, or at least very similar, processing elements (120) organized in a regular grid. Each processing element (120) is capable of executing the desired functionality of the processor. The processing elements (120) are interconnected by a configurable interconnection network (140) and are controlled by a program sequencing issuing device (160) capable of handling exceptions in the instruction flow through the processing elements (120). Consequently, the integrated circuit (100) can be easily redesigned, thus reducing design effort and time-to-market for such architectures.

Abstract: A processor comprises a main controller (CTR11) and a plurality of processing units (1-9). Each processing unit (1-9) has a local controller (CTR1- CTR9) and at least one functional unit (FU1-FU9) controllable by the local controller (CTR1-CTR9). The local controller (CTR1-CTR9) of a processing unit (1-9) is coupled (15) to the main controller (CTR11). The processor further comprises an instruction set, having at least one instruction for increasing the activity of at least one processing unit (1-9). The main controller (CTR11) is arranged to process the at least one instruction for increasing the activity of at least one processing unit (1-9). One or more processing units (1-9) of the processor can be completely switched off, including the corresponding local controller (CTR1-CTR9), since the instructions for switching on a processing unit (1-9) are not processed by the corresponding local controller (CTR1-CTR9), but by the main controller (CTR11) itself.

Abstract: The present invention relates to a processing method and apparatus for implementing a systolic-array-like structure. Input data are stored in a depth-configurable register means (DCF) in a predetermined sequence, and are supplied to a processing means (FU) for processing said input data based on control signals generated from instruction data, wherein the depth of the register means (DCF) is controlled in accordance with the instruction data. Thereby, systolic arrays can be mapped onto a programmable processor, e.g. a VLIW processor, without the need for explicitly issuing operations to implement the register moves that constitute the delay lines of the array.

Abstract: A processor contains a configurable functional unit that is capable of executing reconfigurable instructions, whose effect can be redefined at run-time by loading a configuration program. Reconfigurable instructions are selected in combinations of more than one different reconfigurable instruction. A respective configuration program is generated for each combination of instructions. Each time when an instruction from one of the combinations is needed during execution and the configurable functional unit is not configured with the configuration program for that combination, the configuration program for all of the instructions of that combination into the configurable functional unit. The reconfigurable instruction selects which instruction of the combination is executed.

Abstract: A programmable cell comprises an externally loadable electrically erasable (EE) transistor cell that is configured to be independent of the currently active state of the programmed cell. When all of the EE cells are loaded with a new configuration, the contents of all of the EE cells are loaded into the corresponding programmable cells, preferably within one clock cycle. Because the entirety of the programmable cells can be pre-loaded with the new configuration, the time to effect a reconfiguration is one clock cycle. Because an EE cell is significantly smaller than a conventional four to six transistor storage cell, the area required to implement this single-clock-cycle reconfiguration capability is substantially less than traditional dynamically reprogrammable memory configurations. In an alternative embodiment, multiple EE cells can be associated with each programmable cell, thereby allowing a multiple-configuration capability.

Abstract: A data processing apparatus is capable of executing an operation that requires many more operands than can be provided in a single instruction. An original instruction starts execution of the operation and other, operand supplying instructions that follow each other in time are used to supply the operands for that operation. When such an operand supplying instruction is not supplied in time, execution of the original instruction is suspended.

Abstract: A data processing device has a configurable functional unit for executing an instruction according to a configurable function. The configurable functional unit has a plurality of independent configurable logic blocks for performing programmable logic operations to implement the configurable function. Configurable connection circuits are provided between the configurable logic blocks and both the inputs and the outputs of the configurable functional unit. This allows an optimalization of the distribution of logic functions over the configurable logic blocks.