Patents by Inventor Bernardo Gallegos

Bernardo Gallegos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11848258
    Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.
    Type: Grant
    Filed: December 31, 2020
    Date of Patent: December 19, 2023
    Assignee: Texas Instruments Incorporated
    Inventors: Nazila Dadvand, Bernardo Gallegos
  • Publication number: 20220208665
    Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.
    Type: Application
    Filed: December 31, 2020
    Publication date: June 30, 2022
    Inventors: Nazila Dadvand, Bernardo Gallegos
  • Publication number: 20220210911
    Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.
    Type: Application
    Filed: March 31, 2021
    Publication date: June 30, 2022
    Inventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
  • Patent number: 11244881
    Abstract: A package comprises a molding and a conductive terminal in contact with the molding and having a first surface exposed to a first surface of the molding. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventor: Bernardo Gallegos
  • Publication number: 20210098322
    Abstract: In some examples, a package comprises a molding and a conductive terminal in contact with the molding and having a first surface exposed to a first surface of the molding. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Inventor: Bernardo GALLEGOS
  • Patent number: 10672692
    Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.
    Type: Grant
    Filed: November 21, 2017
    Date of Patent: June 2, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
  • Publication number: 20200135627
    Abstract: A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump.
    Type: Application
    Filed: October 30, 2018
    Publication date: April 30, 2020
    Inventors: Bernardo GALLEGOS, Madison KOZIOL
  • Publication number: 20180096860
    Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.
    Type: Application
    Filed: November 21, 2017
    Publication date: April 5, 2018
    Inventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
  • Publication number: 20180096859
    Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.
    Type: Application
    Filed: September 30, 2016
    Publication date: April 5, 2018
    Inventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
  • Patent number: 9934989
    Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.
    Type: Grant
    Filed: September 30, 2016
    Date of Patent: April 3, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
  • Patent number: 9875930
    Abstract: Methods of packaging integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: January 23, 2018
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernardo Gallegos, Abram Castro
  • Patent number: 9536781
    Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.
    Type: Grant
    Filed: August 20, 2015
    Date of Patent: January 3, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernardo Gallegos, Abram Castro
  • Patent number: 9373572
    Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.
    Type: Grant
    Filed: October 9, 2015
    Date of Patent: June 21, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
  • Publication number: 20160035655
    Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.
    Type: Application
    Filed: October 9, 2015
    Publication date: February 4, 2016
    Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
  • Publication number: 20150357238
    Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.
    Type: Application
    Filed: August 20, 2015
    Publication date: December 10, 2015
    Inventors: Bernardo Gallegos, Abram Castro
  • Patent number: 9165873
    Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.
    Type: Grant
    Filed: September 24, 2014
    Date of Patent: October 20, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
  • Patent number: 9142472
    Abstract: Integrated circuits and methods of fabricating integrated circuits are disclosed herein. One embodiment of an integrated circuit includes a die having a side, wherein a conductive stud extends substantially normal relative to the side. A dielectric layer having a first side and a second side is located proximate the side of the die so that the first side of the dielectric layer is adjacent the side of the die. The conductive stud extends into the first side of the dielectric layer. A first via extends between the conductive stud and the second side of the dielectric layer. A conductive layer having a first side and a second side is located adjacent the second side of the dielectric layer, wherein the first side of the conductive layer is located adjacent the second side of the dielectric layer. At least a portion of the conductive layer is electrically connected to the first via.
    Type: Grant
    Filed: May 25, 2012
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernardo Gallegos, Abram Castro
  • Patent number: 9142496
    Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed.
    Type: Grant
    Filed: July 28, 2014
    Date of Patent: September 22, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
  • Patent number: 9054092
    Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: June 9, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Bernardo Gallegos, Yong Lin
  • Publication number: 20150115421
    Abstract: A method and apparatus of minimizing resin bleed and mold flash on integrated lead finishes by providing groves on the external leads that can control the length of resin bleed.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Inventors: Bernardo Gallegos, Yong Lin