Patents by Inventor Bernardo Gallegos
Bernardo Gallegos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240224415Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.Type: ApplicationFiled: March 12, 2024Publication date: July 4, 2024Inventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
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Publication number: 20240153853Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.Type: ApplicationFiled: December 19, 2023Publication date: May 9, 2024Inventors: Nazila Dadvand, Bernardo Gallegos
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Patent number: 11930590Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.Type: GrantFiled: March 31, 2021Date of Patent: March 12, 2024Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
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Patent number: 11848258Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.Type: GrantFiled: December 31, 2020Date of Patent: December 19, 2023Assignee: Texas Instruments IncorporatedInventors: Nazila Dadvand, Bernardo Gallegos
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Publication number: 20220210911Abstract: In a described example, an apparatus includes: a package substrate having a planar die mount surface; recesses extending into the planar die mount surface; and a semiconductor device die flip chip mounted to the package substrate on the planar die mount surface, the semiconductor device die having post connects having proximate ends on bond pads on an active surface of the semiconductor device die, and extending to distal ends away from the semiconductor device die having solder bumps, wherein the solder bumps form solder joints to the package substrate within the recesses.Type: ApplicationFiled: March 31, 2021Publication date: June 30, 2022Inventors: Tianyi Luo, Osvaldo Jorge Lopez, Jonathan Almeria Noquil, Satyendra Singh Chauhan, Bernardo Gallegos
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Publication number: 20220208665Abstract: A semiconductor package includes a pad and leads, the pad and leads including a base metal predominantly including copper, a first plated metal layer predominantly including nickel in contact with the base metal, and a second plated metal layer predominantly including silver in contact with the first plated metal layer. The first plated metal layer has a first plated metal layer thickness of 0.1 to 5 microns, and the second plated metal layer has a second plated metal layer thickness of 0.2 to 5 microns. The semiconductor package further includes an adhesion promotion coating predominantly including silver oxide in contact with the second plated metal layer opposite the first plated metal layer, a semiconductor die mounted on the pad, a wire bond extending between the semiconductor die and a lead of the leads, and a mold compound covering the semiconductor die and the wire bond.Type: ApplicationFiled: December 31, 2020Publication date: June 30, 2022Inventors: Nazila Dadvand, Bernardo Gallegos
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Patent number: 11244881Abstract: A package comprises a molding and a conductive terminal in contact with the molding and having a first surface exposed to a first surface of the molding. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.Type: GrantFiled: September 30, 2019Date of Patent: February 8, 2022Assignee: TEXAS INSTRUMENTS INCORPORATEDInventor: Bernardo Gallegos
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Publication number: 20210098322Abstract: In some examples, a package comprises a molding and a conductive terminal in contact with the molding and having a first surface exposed to a first surface of the molding. The conductive terminal includes a cavity having a first portion extending along at least half of the first surface of the conductive terminal and a second portion extending along less than half of the first surface of the conductive terminal.Type: ApplicationFiled: September 30, 2019Publication date: April 1, 2021Inventor: Bernardo GALLEGOS
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Patent number: 10672692Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.Type: GrantFiled: November 21, 2017Date of Patent: June 2, 2020Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
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Publication number: 20200135627Abstract: A system comprises a substrate. The substrate comprises a lead. The system also comprises a solder barrier formed on the lead. The solder barrier is to contain a solder bump within a solder area on the lead. The system further includes a solder bump in the solder area and a die having an active surface coupled to the solder bump.Type: ApplicationFiled: October 30, 2018Publication date: April 30, 2020Inventors: Bernardo GALLEGOS, Madison KOZIOL
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Publication number: 20180096859Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.Type: ApplicationFiled: September 30, 2016Publication date: April 5, 2018Inventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
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Publication number: 20180096860Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.Type: ApplicationFiled: November 21, 2017Publication date: April 5, 2018Inventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
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Patent number: 9934989Abstract: A lead frame that is partially covered with an adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame and using a photo-imageable polyimide or epoxy material to form the adhesion layer. A method for forming a lead frame with an adhesion layer starting with a lead frame blank and using a photo-imageable polyimide or epoxy material to form the adhesion layer.Type: GrantFiled: September 30, 2016Date of Patent: April 3, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Jaimal Mallory Williamson, Bernardo Gallegos, Jose Carlos Arroyo
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Patent number: 9875930Abstract: Methods of packaging integrated circuits are disclosed herein. In one embodiment of a method. A die having a side is provided. A conductive stud is connected to the side of the die, wherein the conductive stud has a first end that is connected to the die and an opposite second end. The die is encapsulated except for the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud enters the first side of the first dielectric layer. A conductive layer is affixed to the second side of the first dielectric layer. The second side of the conductive stud is affixed to the conductive layer using a conductive adhesive.Type: GrantFiled: December 24, 2014Date of Patent: January 23, 2018Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bernardo Gallegos, Abram Castro
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Patent number: 9536781Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.Type: GrantFiled: August 20, 2015Date of Patent: January 3, 2017Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Bernardo Gallegos, Abram Castro
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Patent number: 9373572Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.Type: GrantFiled: October 9, 2015Date of Patent: June 21, 2016Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
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Publication number: 20160035655Abstract: A packaged semiconductor device including a leadframe and a plurality of angularly shaped capacitors. The leadframe includes structures with surfaces and sidewalls. The angularly shaped capacitors are attached to surface portions of the leadframe structures. The angularly shaped capacitors have sidewalls coplanar with structure sidewalls. The angularly shaped capacitors includes a conductive material attached to the structure surface. The conductive material having pores covered by oxide and filled with conductive polymer. The angularly shaped capacitors topped by electrodes are made of a second metal.Type: ApplicationFiled: October 9, 2015Publication date: February 4, 2016Inventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
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Publication number: 20150357238Abstract: Methods of fabricating integrated circuits are disclosed herein. A die having a side is provided. A conductive stud extends from the side in a direction that is substantially normal to the side. A first dielectric layer is affixed to the side of the die. The first dielectric layer has a first side and a second side. The first side of the first dielectric layer is affixed to the side of the die. The conductive stud pierces the first side of the first dielectric layer. A first via is formed through the first dielectric layer between the conductive stud and the second side. The first via is electrically connected to the conductive stud.Type: ApplicationFiled: August 20, 2015Publication date: December 10, 2015Inventors: Bernardo Gallegos, Abram Castro
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Patent number: 9165873Abstract: A packaged semiconductor device including a leadframe made of a first metal, the leadframe including structures with surfaces and sidewalls; capacitors attached to surface portions of the leadframe structures, the capacitors having sidewalls coplanar with structure sidewalls; the capacitors including a foil of conductive material attached to the structure surface, the conductive material having pores covered by oxide and filled with conductive polymer, the capacitors topped by electrodes made of a second metal.Type: GrantFiled: September 24, 2014Date of Patent: October 20, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott
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Patent number: 9142496Abstract: A method for fabricating a packaged semiconductor device begins by placing a first mask on a foil of porous conductive material bonded on a strip of a first metal. The surface of the conductive material and the inside of the pores are oxidized. The first mask leaves areas unprotected. The pores of the unprotected areas are filled with a conductive polymeric compound. A layer of a second metal is deposited on the conductive polymeric compound in the unprotected areas. The first mask is removed to expose un-oxidized conductive material. The foil thickness of the un-oxidized conductive material is removed to expose the underlying first metal. This creates sidewalls of the foil and leaves un-removed the capacitor areas covered by the second metal. A second mask is placed on the strip, the second mask defines a plurality of leadframes having chip pads and leads, and protecting the capacitor areas. The portions of the first metal exposed by the second mask are removed.Type: GrantFiled: July 28, 2014Date of Patent: September 22, 2015Assignee: TEXAS INSTRUMENTS INCORPORATEDInventors: Gregory E. Howard, Bernardo Gallegos, Rajiv Dunne, Darvin R. Edwards, Siva P. Gurrum, Manu J. Prakuzhy, Donald C. Abbott