Abstract: An automated machine wherein messages exchanged between components of the machine are forwarded to at least one component at a first time point that temporarily stores them and from that component to a central unit at a second time point is disclosed. Said first time point preceding said second time point within the framework of a cycle time of the automated machine. The time points are determined relative to that cycle time and provided to respective components in conjunction with a startup of the automated machine. The component temporarily storing messages forwards them in the manner of a layer-3 switch. This message forwarding is driven by the respective time points, rather than event-driven, can operate seamlessly in existing systems wherein communications are time-slot controlled, and decouples the components so that real-time communications within the machine can be optimized.

Abstract: An automated machine wherein messages exchanged between components of the machine are forwarded to at least one component at a first time point that temporarily stores them and from that component to a central unit at a second time point is disclosed. Said first time point preceding said second time point within the framework of a cycle time of the automated machine. The time points are determined relative to that cycle time and provided to respective components in conjunction with a startup of the automated machine. The component temporarily storing messages forwards them in the manner of a layer-3 switch. This message forwarding is driven by the respective time points, rather than event-driven, can operate seamlessly in existing systems wherein communications are time-slot controlled, and decouples the components so that real-time communications within the machine can be optimized.

Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Abstract: A method and apparatus for frame synchronization in digital communication systems using multiple modulation formats, including the Differential Phase Shift Keying (DPSK), Duobinary Signaling (DBS), and ON/OFF Keying (OOK) modulation formats, perform a search for both a frame alignment sequence (FAS) and the inverted FAS and determine the polarity of the received digital stream.

Abstract: Bit error patterns for high speed data systems are generated by randomly distributing a first error pattern of G bits, output from a group of substantially uncorrelated bit error generators, into a second error pattern of N bits, where G and N are integers and G is less than or equal to N. In one embodiment, G bit error generators produce a G bit error pattern per bit period. Each bit error generator operates at a prescribed bit error rate. A distribution element randomly rearranges the order and placement of the G bits produced during a single bit period within an N bit grouping. The N bit group corresponds to N consecutive bits of data with which the error bits can be combined. Each bit error generator can be realized by a linear feedback shift register or its equivalent. Different primitive polynomials and different lengths can be used for each linear feedback shift register. In addition, outputs from fewer than all the shift register stages are utilized to generate each error bit.

Abstract: A combiner (CMB) comprises a number (K) of subprocessing units (S1, S2, Sk) which each combine digital data values from input data sets with a higher processing rate. A single selector (M3) is used for cyclically reading out the addition results from the respective subprocessing units (SU1, . . . ,SUk). The invention allows to flexibly combine data from any desired input onto a specific output.