Patents by Inventor Bernd Foeste
Bernd Foeste has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9527725Abstract: A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.Type: GrantFiled: April 16, 2014Date of Patent: December 27, 2016Assignee: Infineon Technologies AGInventors: Boris Binder, Bernd Foeste, Thoralf Kautzsch, Stefan Kolb, Marco Mueller
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Patent number: 8921954Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.Type: GrantFiled: August 22, 2013Date of Patent: December 30, 2014Assignee: Infineon Technologies AGInventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
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Publication number: 20140227818Abstract: A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.Type: ApplicationFiled: April 16, 2014Publication date: August 14, 2014Applicant: Infineon Technologies AGInventors: Boris Binder, Bernd Foeste, Thoralf Kautzsch, Stefan Kolb, Marco Mueller
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Patent number: 8723276Abstract: A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.Type: GrantFiled: October 5, 2010Date of Patent: May 13, 2014Assignee: Infineon Technologies AGInventors: Boris Binder, Bernd Foeste, Thoralf Kautzsch, Stefan Kolb, Marco Mueller
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Patent number: 8627720Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor mass element configured to move in response to an applied acceleration. The mass element is defined by trenches etched into the semiconductor substrate and a cavity below the mass element. The semiconductor device includes a sensing element configured to sense movement of the mass element.Type: GrantFiled: September 12, 2012Date of Patent: January 14, 2014Assignee: Infineon Technologies AGInventors: Thoralf Kautzsch, Bernhard Winkler, Dirk Meinhold, Ben Rosam, Bernd Foeste, Andreas Thamm, Boris Binder
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Publication number: 20130334624Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.Type: ApplicationFiled: August 22, 2013Publication date: December 19, 2013Applicant: Infineon Technologies AGInventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
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Patent number: 8518732Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.Type: GrantFiled: December 22, 2010Date of Patent: August 27, 2013Assignee: Infineon Technologies AGInventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
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Publication number: 20130001712Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor mass element configured to move in response to an applied acceleration. The mass element is defined by trenches etched into the semiconductor substrate and a cavity below the mass element. The semiconductor device includes a sensing element configured to sense movement of the mass element.Type: ApplicationFiled: September 12, 2012Publication date: January 3, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Thoralf Kautzsch, Bernhard Winkler, Dirk Meinhold, Ben Rosam, Bernd Foeste, Andreas Thamm, Boris Binder
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Patent number: 8266962Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor mass element configured to move in response to an applied acceleration. The mass element is defined by trenches etched into the semiconductor substrate and a cavity below the mass element. The semiconductor device includes a sensing element configured to sense movement of the mass element and a complementary metal-oxide-semiconductor (CMOS) circuit formed on the substrate.Type: GrantFiled: January 28, 2009Date of Patent: September 18, 2012Assignee: Infineon Technologies AGInventors: Thoralf Kautzsch, Bernhard Winkler, Dirk Meinhold, Ben Rosam, Bernd Foeste, Andreas Thamm, Boris Binder
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Publication number: 20120161254Abstract: A method for providing a semiconductor structure includes forming a sacrificial structure by etching a plurality of trenches from a first main surface of a substrate. The method further includes covering the plurality of trenches at the first main surface with a cover material to define cavities within the substrate, removing a part of the substrate from a second main surface opposite to the first main surface to a depth at which the plurality of trenches are present, and etching away the sacrificial structure from the second main surface of the substrate.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: Infineon Technologies AGInventors: Thoralf Kautzsch, Stefan Kolb, Boris Binder, Bernd Foeste, Marco Mueller
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Patent number: 8008161Abstract: A method for fabricating a capacitor arrangement which includes at least three electrodes is described. The capacitor arrangement is fabricated using a number of lithography methods that is smaller than the number of electrodes. A capacitor arrangement extending over more than two or more interlayers between metallization layers has a high capacitance per unit area and can be fabricated in a simple way is also described. The circuit arrangement has a high capacitance per unit area and can be fabricated in a simple way. An electrode layer is first patterned using a dry-etching process and residues of the electrode layer are removed using a wet-chemical process, making it possible to fabricate capacitors with excellent electrical properties.Type: GrantFiled: June 20, 2005Date of Patent: August 30, 2011Assignee: Infineon Technologies AGInventors: Jens Bachmann, Bernd Föste, Klaus Goller, Jakob Kriz
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Publication number: 20110068420Abstract: A method for fabricating a semiconductor structure includes etching a first opening into a substrate; etching a chip singulation trench into the substrate to define a lamella between the first opening and the chip singulation trench; fabricating a sense element for sensing a deflection of the lamella; and singulating the semiconductor structure at the chip singulation trench.Type: ApplicationFiled: October 5, 2010Publication date: March 24, 2011Applicant: Infineon Technologies AGInventors: Boris Binder, Bernd Foeste, Thoralf Kautzsch, Stefan Kolb, Marco Mueller
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Patent number: 7832279Abstract: A semiconductor device includes a first cavity within a semiconductor substrate and a second cavity within the semiconductor substrate. The second cavity is open to an atmosphere and defines a first lamella between the first cavity and the second cavity. The semiconductor device includes a first sense element configured for sensing a pressure on the first lamella.Type: GrantFiled: September 11, 2008Date of Patent: November 16, 2010Assignee: Infineon Technologies AGInventors: Thoralf Kautzsch, Boris Binder, Dirk Meinhold, Ben Rosam, Bernd Foeste, Andreas Thamm
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Publication number: 20100186511Abstract: A semiconductor device includes a semiconductor substrate and a semiconductor mass element configured to move in response to an applied acceleration. The mass element is defined by trenches etched into the semiconductor substrate and a cavity below the mass element. The semiconductor device includes a sensing element configured to sense movement of the mass element and a complementary metal-oxide-semiconductor (CMOS) circuit formed on the substrate.Type: ApplicationFiled: January 28, 2009Publication date: July 29, 2010Applicant: Infineon Technologies AGInventors: Thoralf Kautzsch, Bernhard Winkler, Dirk Meinhold, Ben Rosam, Bernd Foeste, Andreas Thamm, Boris Binder
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Patent number: 7711998Abstract: A test circuit arrangement for testing latch units is provided which includes a) a voltage generator configured to adjust a voltage potential difference between a first ground line and a second ground line of the latch units and/or to adjust a voltage potential difference between a first supply voltage line and a second supply voltage line of the latch units; b) combiner configured to combine logical outputs of the latch units; and c) determiner configured to determine the voltage potential difference between the first ground line and the second ground line and/or the voltage potential difference between the first supply voltage line and the second supply voltage line in a state when all of the latch units have identical logical outputs.Type: GrantFiled: March 30, 2007Date of Patent: May 4, 2010Assignee: Infineon Technologies AGInventor: Bernd Foeste
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Publication number: 20100058876Abstract: A semiconductor device includes a first cavity within a semiconductor substrate and a second cavity within the semiconductor substrate. The second cavity is open to an atmosphere and defines a first lamella between the first cavity and the second cavity. The semiconductor device includes a first sense element configured for sensing a pressure on the first lamella.Type: ApplicationFiled: September 11, 2008Publication date: March 11, 2010Applicant: Infineon Technologies AGInventors: Thoralf Kautzsch, Boris Binder, Dirk Meinhold, Ben Rosam, Bernd Foeste, Andreas Thamm
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Publication number: 20080238437Abstract: A test circuit arrangement for testing latch units is provided which includes a) a voltage generator configured to adjust a voltage potential difference between a first ground line and a second ground line of the latch units and/or to adjust a voltage potential difference between a first supply voltage line and a second supply voltage line of the latch units; b) combiner configured to combine logical outputs of the latch units; and c) determiner configured to determine the voltage potential difference between the first ground line and the second ground line and/or the voltage potential difference between the first supply voltage line and the second supply voltage line in a state when all of the latch units have identical logical outputs.Type: ApplicationFiled: March 30, 2007Publication date: October 2, 2008Applicant: INFINEON TECHNOLOGIES AGInventor: BERND FOESTE