Abstract: Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Abstract: Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

Abstract: A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Abstract: Transformer circuitry comprising: a transformer having a primary coil and a secondary coil, the primary coil having first and second primary terminals and the secondary coil having first and second secondary terminals, and a secondary coil driver configured to drive a secondary voltage signal V2 across the secondary terminals which has a target relationship with a primary voltage signal V1 driven across the primary terminals by a primary coil driver so that an inductance value measured between the primary terminals is governed by the target relationship.

Abstract: A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.

Abstract: An inductor arrangement, comprising: a first pair of driven inductors configured to be driven to generate magnetic fields which are substantially in antiphase, and arranged relative to one another so that their magnetic fields substantially cancel one another at a first null line between those inductors; and a second pair of driven inductors configured to produce magnetic fields which are substantially in antiphase, and arranged relative to one another so that their magnetic fields substantially cancel one another at a second null line between those inductors, wherein the pairs of driven inductors are arranged relative to one another so that the first and second null lines intersect one another, with the first pair of driven inductors located substantially on the second null line and the second pair of inductors located substantially on the first null line.

Abstract: Transformer circuitry comprising: a transformer having a primary coil and a secondary coil, the primary coil having first and second primary terminals and the secondary coil having first and second secondary terminals, and a secondary coil driver configured to drive a secondary voltage signal V2 across the secondary terminals which has a target relationship with a primary voltage signal V1 driven across the primary terminals by a primary coil driver so that an inductance value measured between the primary terminals is governed by the target relationship.

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

Abstract: In semiconductor integrated circuitry having metal layers and via layers sandwiched between adjacent said metal layers, a capacitor is formed from metal structures implemented in first to third metal layers. The metal structures comprise strips having widths parallel to the layers. The strips of the first layer form a first comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips being in a lower range of widths. The strips of the second layer form a second comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips being in the lower range of widths. The width of each base strip formed in the second layer is in an intermediate range of widths; and the strips formed in the third layer have widths in a higher range of widths.

Abstract: In semiconductor integrated circuitry having metal layers and via layers sandwiched between adjacent said metal layers, a capacitor is formed from metal structures implemented in first to third metal layers. The metal structures comprise strips having widths parallel to the layers. The strips of the first layer form a first comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips being in a lower range of widths. The strips of the second layer form a second comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips being in the lower range of widths. The width of each base strip formed in the second layer is in an intermediate range of widths; and the strips formed in the third layer have widths in a higher range of widths.

Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.

Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.