Abstract: A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.

Abstract: A method includes forming a diffusion barrier over a semiconductor structure. The formation of the diffusion barrier includes performing a first tantalum deposition process, the first tantalum deposition process forming a first tantalum layer over the semiconductor structure, performing a treatment of the first tantalum layer, and performing a second tantalum deposition process after the treatment of the first tantalum layer. The treatment modifies at least a portion of the first tantalum layer. The second tantalum deposition process forms a second tantalum layer over the first tantalum layer.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

Abstract: Methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming a barrier layer overlying a metal line of a metallization layer above a semiconductor substrate using an atomic layer deposition (ALD) process and a physical vapor deposition (PVD) process. A liner-forming material is deposited overlying the barrier layer to form a liner. A conductive metal is deposited overlying the liner.

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.

Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

Abstract: A method of providing a semiconductor structure comprising a diffusion barrier layer and a seed layer, the seed layer comprising an alloy of copper and a metal other than copper, depositing an electrically conductive material on the seed layer, performing an annealing process, wherein at least a first portion of the metal other than copper diffuses away from a vicinity of the diffusion barrier layer through the electrically conductive material, and wherein, in case of a defect in the diffusion barrier layer, a second portion of the metal other than copper indicative of the defect remains in a vicinity of the defect, measuring a distribution of the metal other than copper in at least a portion of the semiconductor structure, and determining, from the measured distribution of the metal other than copper, if the second portion of the metal other than copper is present.

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes an electrically conductive feature including a first metal, a dielectric material provided over the electrically conductive feature and a hardmask. The hardmask includes a hardmask material and is provided over the dielectric material. An opening is provided in the interlayer dielectric and the hardmask. A portion of the electrically conductive feature is exposed at a bottom of the opening. The hardmask is removed. The removal of the hardmask includes exposing the semiconductor structure to an etching solution including hydrogen peroxide and a corrosion inhibitor. After the removal of the hardmask, the semiconductor structure is rinsed. Rinsing the semiconductor structure includes exposing the semiconductor structure to an alkaline rinse solution.

Abstract: A method includes providing a semiconductor structure. The semiconductor structure includes a substrate having a frontside and a backside, an electrically conductive feature including copper provided at the frontside of the substrate and a low-k interlayer dielectric provided over the electrically conductive feature. A portion of the interlayer dielectric is etched. In the etch process, a surface of the electrically conductive feature is exposed. A degas process is performed, wherein the semiconductor structure is exposed to a first gas, and wherein the semiconductor structure is heated from the backside and from the frontside. A preclean process may be performed. The preclean process may include a first phase wherein the semiconductor structure is exposed to a substantially non-ionized second gas and a second phase wherein the semiconductor structure is exposed to a plasma created from the second gas.

Abstract: One illustrative method disclosed herein includes forming a trench/via in a layer of insulating material, forming a barrier layer in at least the trench/via, after forming said barrier layer, performing at least one process operation to introduce manganese into the barrier layer and thereby define a manganese-containing barrier layer, forming a substantially pure copper-based seed layer above the manganese-containing barrier layer, depositing a bulk copper-based material above the copper-based seed layer so as to overfill the trench/via, and removing excess materials positioned outside of the trench/via to thereby define a copper-based conductive structure.

Abstract: Processes for forming an integrated circuit are provided. In an embodiment, a process for forming an integrated circuit includes forming a low-k dielectric layer overlying a base substrate. An etch mask is patterned over the low-k dielectric layer. A recess is etched into the low-k dielectric layer through the etch mask to expose a recess surface within the recess. The low-k dielectric layer and the base substrate are annealed after etching. Annealing is conducted in an annealing environment, such as in an annealing furnace that provides the annealing environment. The recess surface is exposed to the annealing environment. An electrically-conductive material is deposited in the recess after annealing to form an embedded electrical interconnect.

Abstract: Disclosed herein are various methods of forming metal nitride layers on various types of semiconductor devices. In one example, the method includes forming a layer of insulating material above a semiconducting substrate, performing a physical vapor deposition process to form a metal nitride layer above the layer of insulating material, wherein the metal nitride layer has an intrinsic as-deposited stress level, and performing at least one process operation on the metal nitride layer to reduce a magnitude of the intrinsic as-deposited stress level in the metal nitride layer.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: One embodiment relates to an integrated circuit formed on a semiconductor body having interconnect between source/drain regions of a first and second transistor. The interconnect includes a metal body arranged underneath the surface of the semiconductor body. A contact element establishes electrical contact between the metal body and the source/drain regions of the first and second transistor. The contact element extends along a connecting path between the source/drain regions of the first and second transistors. Other methods, devices, and systems are also disclosed.

Abstract: In a method for producing a conductive layer a substrate is provided. On the substrate, a layer includes at least two different metal nitrides. In one embodiment, on a surface of the substrate a first metal nitride layer is deposited, followed by a second metal nitride layer formed thereon. A third metal layer is then deposited on a surface of the second metal nitride layer.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.

Abstract: A method of fabricating an integrated circuit, including a functional layer on a substrate is disclosed. One embodiment includes providing a substrate in a process atmosphere. A first precursor and a second precursor are provided in the process atmosphere. The first precursor is removed from the process atmosphere. A third precursor is provided in the process atmosphere.

Abstract: A dielectric interlayer, especially for a storage capacitor, is formed from a layer sequence subjected to a temperature process, wherein the layer sequence has at least a first metal oxide layer and a second metal oxide layer formed by completely oxidizing a metal nitride layer to higher valency.