Patents by Inventor Bernd K. Appelt
Bernd K. Appelt has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20130037929Abstract: The present semiconductor device packages include a die, a redistribution layer and a plurality of conductive pillars electrically connected to the redistribution layer. A molding compound partially encapsulates the die and the pillars. A plurality of interconnect patterns on the molding compound are electrically connected to the pillars. The interconnect patterns provide electrical connections for a second, stacked semiconductor package.Type: ApplicationFiled: August 9, 2011Publication date: February 14, 2013Inventors: Kay S. Essig, Bernd K. Appelt
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Patent number: 6815085Abstract: A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.Type: GrantFiled: May 12, 2003Date of Patent: November 9, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, John M. Lauffer
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Patent number: 6781064Abstract: A printed circuit board for use in an electronic device package such as a ball grid array package or organic chip carrier package. This printed circuit board includes a glass-free dielectric for separating and insulating power cores, circuitry or plated through holes from each other to prevent shorts caused by a migration of conductive material along glass-based prepreg substrates.Type: GrantFiled: June 29, 1999Date of Patent: August 24, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Anilkumar C. Bhatt, James W. Fuller, Jr., John M. Lauffer, Voya R. Markovich, William J. Rudik, William E. Wilson
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Patent number: 6739046Abstract: A method is provided for connecting two conductive surfaces in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive surface, applying a dielectric insulation material over the first conductive surface such that the dendrites are exposed through the insulation material to leave a substantially planar surface of exposed dendrites, and placing a second conductive surface on top of the exposed dendrites. The second conductive surface may be a surface metal, a chip bump array, or a ball grid array. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection and planarization manufactured in accordance with the present invention.Type: GrantFiled: May 22, 2000Date of Patent: May 25, 2004Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20030202314Abstract: A capacitive element for a circuit board or chip carrier is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The partially cured sheet is laminated to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils. The use of two or more sheets of dielectric material makes it very unlikely that two or more defects in the sheets of dielectric material will align, thus greatly reducing the probability of a defect causing a failure in test or field use.Type: ApplicationFiled: May 12, 2003Publication date: October 30, 2003Applicant: International Business Machines CorporationInventors: Bernd K., Appelt, John M. Lauffer
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Patent number: 6625857Abstract: A method of forming a capacitive element for a circuit board or chip carrier having improved capacitance is provided. The element is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured followed by being fully cured. The lamination takes place by laminating a partially cured sheet to at least one other sheet of dielectric material and one of the conductive sheets. The total thickness of the two sheets of the dielectric component does not exceed about 4 rolls and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.Type: GrantFiled: February 1, 2001Date of Patent: September 30, 2003Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, John M. Lauffer
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Publication number: 20030162047Abstract: The present invention provides a unique conductive composition for filling vias or through holes to make reliable vertical or Z-connects. The through holes may be plated or unplated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.Type: ApplicationFiled: February 27, 2003Publication date: August 28, 2003Applicant: International Business Machines CorporationInventors: Bernd K. Appelt, Jeffrey D. Gelorme, Sung Kwon Kang, Voya R. Markovich, Kostas Papathomas, Sampath Purushothaman
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Patent number: 6574090Abstract: A capacitive element for a circuit board or chip carrier having improved capacitance and method of manufacturing the same is provided. The structure is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured or softened followed by being fully cured or hardened. The lamination takes place by laminating a partially cured or softened sheet to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.Type: GrantFiled: March 30, 2001Date of Patent: June 3, 2003Assignee: International Business Machines CorporatiionInventors: Bernd K. Appelt, John M. Lauffer
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Patent number: 6555762Abstract: The present invention provides a unique, high density, electronic package having a conductive composition for filling vias or through holes to make reliable vertical or Z-connects from a dielectric layer to adjacent electrical circuits. The through holes may be plated or non-plated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.Type: GrantFiled: July 1, 1999Date of Patent: April 29, 2003Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Jeffrey D. Gelorme, Sung Kwon Kang, Voya R. Markovich, Kostas Papathomas, Sampath Purushothaman
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Publication number: 20030006066Abstract: The present invention provides a unique conductive composition for filling vias or through holes to make reliable vertical or Z-connects. The through holes may be plated or unplated prior to filling. A description for making high density electronic packaging using this feature is also disclosed.Type: ApplicationFiled: July 1, 1999Publication date: January 9, 2003Inventors: BERND K. APPELT, JEFFREY D. GELORME, SUNG KWON KANG, VOYA R. MARKOVICH, KOSTAS PAPATHOMAS, SAMPATH PURUSHOTHAMAN
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Patent number: 6427323Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: GrantFiled: May 17, 2001Date of Patent: August 6, 2002Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Patent number: 6420253Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.Type: GrantFiled: June 14, 2001Date of Patent: July 16, 2002Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Gary A. Johansson, Gerald W. Jones, Luis J. Matienzo, Yenloan H. Nguyen, Konstantinos I. Papathomas
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Patent number: 6391210Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.Type: GrantFiled: July 9, 2001Date of Patent: May 21, 2002Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, John M. Lauffer, Voya R. Markovich, Irving Memis, David J. Russell
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Publication number: 20010042733Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.Type: ApplicationFiled: July 9, 2001Publication date: November 22, 2001Inventors: Bernd K. Appelt, John M. Lauffer, Voya R. Markovich, Irving Memis, David J. Russell
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Publication number: 20010034937Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: ApplicationFiled: May 17, 2001Publication date: November 1, 2001Applicant: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20010028117Abstract: A method and structure is provided for preventing wetting or bleed of an adhesive, such as an epoxy, onto noble metal wire bond pads on the surface of a dielectric substrate when attaching an I/C chip to the substrate. The method includes treating the wire bond pads with a chemical composition which prevents bleeding onto the surfaces of the wire bond pads by a component of the epoxy. The chemical composition is a chemical which will provide “Self-Assembled Monolayers” (SAMs) on the surface of the gold. These compositions are characterized by a molecule having at least one group, such as a mercaptan or disulfide, connected to a hydrocarbon moiety, such as a (CH2)x chain. The affinity of the thiol or sulfur-containing portion of the molecule chemically bonding with the noble metal provides a relatively strong attachment of the molecule to the metal surface.Type: ApplicationFiled: June 14, 2001Publication date: October 11, 2001Applicant: International Business Machines CorporationInventors: Bernd K. Appelt, Gary A. Johansson, Gerald W. Jones, Luis J. Matienzo, Yenloan H. Nguyen, Konstantinos I. Papathomas
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Patent number: 6300575Abstract: A method is provided for connecting two conductive layers in an electronic circuit package comprising the steps of forming dendrites on selected regions of a first conductive layer, forming dendrites on selected regions of a second conductive layer, applying an epoxy adhesive material over the first conductive layer, and compressively attaching the second conductive layer to the first conductive layer such that the dendrites on the first conductive layer contact the dendrites on the second conductive layer. Also claimed is an electronic circuit package incorporating the dendrites used for electrical interconnection manufactured in accordance with the present invention. An alternative embodiment of the invention utilizes an intermediate surface metal with dendrites in place of a “through via.Type: GrantFiled: August 25, 1997Date of Patent: October 9, 2001Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, Saswati Datta, Michael A. Gaynes, John M. Lauffer, James R. Wilcox
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Publication number: 20010022718Abstract: A capacitive element for a circuit board or chip carrier having improved capacitance and method of manufacturing the same is provided. The structure is formed from a pair of conductive sheets having a dielectric component laminated therebetween. The dielectric component is formed of two or more dielectric sheets, at least one of which can be partially cured or softened followed by being fully cured or hardened. The lamination takes place by laminating a partially cured or softened sheet to at least one other sheet of dielectric material and one of the sheets of conductive material. The total thickness of the two sheets of the dielectric component does not exceed about 4 mils and preferably does not exceed about 3 mils; thus, the single dielectric sheet does not exceed about 2 mils and preferably does not exceed about 1.5 mils in thickness.Type: ApplicationFiled: March 30, 2001Publication date: September 20, 2001Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Bernd K. Appelt, John M. Lauffer
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Patent number: 6290860Abstract: A circuit board having a structure including a permanent photoimageable dielectric material suitable for fabrication of vias both by laser ablation, plasma ablation, or mechanical drilling techniques and by photoimaging techniques. A process is also disclosed for the manufacture of a multi-level circuit on a substrate having a first-level circuitry pattern on at least one side. The process comprises applying a permanent photoimageable dielectric over the first-level circuitry pattern; exposing the permanent photoimageable dielectric to radiation; laminating a conductive metal layer to the dielectric; making holes in the conductive metal layer and dielectric by mechanical drilling or by laser or plasma ablation; and making a second-level circuitry pattern and filling the holes with a conductive material to electrically connect the first and second layers of circuitry.Type: GrantFiled: April 1, 1999Date of Patent: September 18, 2001Assignee: International Business Machines CorporationInventors: Bernd K. Appelt, John M. Lauffer, Voya R. Markovich, Irving Memis, David J. Russell
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Publication number: 20010013644Abstract: A substrate that is substantially non-wettable to adhesive resin is disclosed. The substrate is coated with a fluorinated silane composition.Type: ApplicationFiled: March 27, 2001Publication date: August 16, 2001Applicant: International Business Machines CorporationInventors: Konstantinos Papathomas, Bernd K. Appelt, John J. Konrad