Abstract: Techniques are disclosed for determining the likelihood that a known feature in an integrated circuit design will cause a defect during the manufacturing process. According to some of these techniques, various logical units that incorporate an identified design feature are identified, and the amount that the design feature occurs in each of a plurality of these logical units is determined. The failure rate of integrated circuit portions corresponding to at least these logical units are then obtained. A feature failure coefficient indicating the likelihood that the feature will cause a defect then is determined by correlating the failure rates with the amount of occurrences of the feature.

Abstract: A seed skipping mechanism is provided for use in conjunction with a linear feedback shift register used as a pseudo-random pattern generator for generating sequences of test bit streams for testing integrated circuit devices. The utilization of seed skipping for the pseudo-random pattern number generator in connection with weighting of the patterns from the random pattern generator provides an effective and low cost solution to data storage problems associated with generating effective test patterns for testing integrated circuit chip devices.