Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: Disclosed herein are representative embodiments of methods, apparatus, and systems for performing diagnostic from signatures created during circuit testing. For example, in one exemplary method disclosed herein, a signature produced by a signature generator is received. In this embodiment, the signature corresponds to the circuit's response to no more than one test pattern. The signature is compared to entries of a fault dictionary, an entry of the fault dictionary is matched to the signature if the entry identifies a fault that explains the signature, and the fault is stored in a list of fault candidates.

Abstract: An arrangement that will provide multiple communication paths for the simultaneously testing of a plurality of un-diced chips on a semiconductor wafer that will simultaneously permit each such communication path to service more than one chip while using a minimum number of tester contacts. These and other objects, features and advantages of the present invention are accomplished in a semiconductor wafer having thereon a number of kerf isolated integrated chips, each of said chips being coupled to at least two different ones of strategically placed administration circuits via two different stimulus buses; each chip being coupled to each administration circuit via selection control circuits laid down in the kerf area between the chips. It is this redundancy that significantly reduces the possibility of failure associated administration or selection control circuits.

Abstract: A method and apparatus for improving the efficiency of scan testing of integrated circuits is described. This efficiency is achieved by reducing the amount of required test stimulus source data and by increasing the effective bandwidth of the scan-load operation. The reduced test data volume and corresponding test time are achieved by integrating a real-time test data decoder or logic network into each integrated circuit chip.