Patents by Inventor Bernd Kothe

Bernd Kothe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor wafer with electrically connected contact and test areas
    Patent number: 8753901
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Grant
    Filed: July 28, 2011
    Date of Patent: June 17, 2014
    Assignee: Infineon Technologies AG
    Inventors: Ertle Werner, Bernd Goller, Michael Horn, Bernd Kothe
  • SEMICONDUCTOR WAFER WITH ELECTRICALLY CONNECTED CONTACT AND TEST AREAS
    Publication number: 20110294238
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Application
    Filed: July 28, 2011
    Publication date: December 1, 2011
    Applicant: INFINEON TECHNOLOGIES AG
    Inventors: Werner Ertle, Bernd Goller, Michael Horn, Bernd Kothe
  • Semiconductor wafer with electrically connected contact and test areas
    Patent number: 8044394
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Grant
    Filed: July 29, 2003
    Date of Patent: October 25, 2011
    Assignee: Infineon Technologies AG
    Inventors: Werner Ertle, Bernd Goller, Michael Horn, Bernd Kothe
  • Semiconductor wafer with electrically connected contact and test areas
    Publication number: 20060097386
    Abstract: The invention relates to an arrangement of contact areas and test areas on patterned semiconductor chips. The contact areas and the test areas are electrically connected to one another via a conduction web. Whereas the contact areas are arranged in a first region, which has no components of an integrated circuit, the test areas lie in a second region of the top side of the semiconductor chip, which region has components of an integrated circuit.
    Type: Application
    Filed: July 29, 2003
    Publication date: May 11, 2006
    Inventors: Werner Ertle, Bernd Goller, Michael Horn, Bernd Kothe