Abstract: A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

Abstract: A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

Abstract: A semiconductor device is provided, which may include: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate and electrically coupled to the well; and a control gate terminal electrically coupled to the control gate; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage.

Abstract: A device including a first metal feature is disposed in a first insulating layer. A second metal feature is disposed in a second insulating layer and separated from the first metal feature by a portion of a first etch stop liner disposed between the first and the second insulating layers. The second metal feature is capacitively coupled to the first metal feature through the first etch stop liner.

Abstract: An inductor for a semiconductor device is provided, which may include: a plurality of structured metallization layers, wherein the plurality of structured metallization layers includes at least a first metallization layer, a second metallization layer disposed over the first metallization layer, a third metallization layer disposed over the second metallization layer, and a fourth metallization layer disposed over the third metallization layer; wherein a portion of the first metallization layer and a portion of the fourth metallization layer form a first coil; wherein a portion of the second metallization layer and a portion of the third metallization layer form a second coil; and wherein the second coil is arranged within the inner space defined by the first coil.

Abstract: A semiconductor device is provided, which may include: a well of a first conductivity type located within a substrate of a second conductivity type; a well terminal electrically coupled to the well; a floating gate disposed over the well; a floating gate terminal electrically coupled to the floating gate; a control gate disposed over the floating gate and electrically coupled to the well; and a control gate terminal electrically coupled to the control gate; wherein the floating gate terminal is configured to receive a first voltage; wherein the control gate terminal and the well terminal are configured to receive a second voltage.