Abstract: A test equipment has a signal input/signal output and a use-site calibration unit for determining a user-site compensation function. The user-site compensation function has a compensation magnitude function and a compensation Hilbert phase function. The calibration unit has a level meter and a calculator. The level meter is configured to measure a magnitude characteristic of the electrical signal, the magnitude characteristic being the basis for the determination of the compensation Hilbert phase function. The calculator is configured to determine a Hilbert phase characteristic of the electrical signal based on a Hilbert transformation of a function dependent on the measured magnitude characteristic and to determine the compensation Hilbert phase function on the basis of the Hilbert phase characteristic.

Abstract: An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.

Abstract: An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.

Abstract: A test equipment has a signal input/signal output and a use-site calibration unit for determining a user-site compensation function. The user-site compensation function has a compensation magnitude function and a compensation Hilbert phase function. The calibration unit has a level meter and a calculator. The level meter is configured to measure a magnitude characteristic of the electrical signal, the magnitude characteristic being the basis for the determination of the compensation Hilbert phase function. The calculator is configured to determine a Hilbert phase characteristic of the electrical signal based on a Hilbert transformation of a function dependent on the measured magnitude characteristic and to determine the compensation Hilbert phase function on the basis of the Hilbert phase characteristic.

Abstract: An automated test equipment for analyzing an analog time domain output signal of an electronic device under test includes: an analog-to-digital converter configured for converting an analog time domain signal; a sampling clock configured for producing a clock signal; a time-to-frequency converter configured for converting the digital time domain signal into a digital frequency domain signal so that the digital frequency domain signal is represented by frequency bins; a memory device configured for storing a set of empirically determined operating parameters; and a jitter components removal module for removing jitter components produced by the analog-to-digital converter, wherein the jitter removal module is configured for subtracting the lower spur and the upper spur of each frequency bin of the frequency bins from the digital frequency domain signal so that the cleaned digital frequency domain signal is produced.

Abstract: An automated test equipment for testing a device under test includes a control unit and a plurality of tester subunits. The control unit is configured to put the tester subunits in a state of lower activity in dependence on a current demand on the test resources.

Abstract: An automatic tester, comprising a first signal converter, a first signal path, and a second signal path. The first signal converter is operable to convert, using a conversion clock signal, a signal from a digital signal domain to an analog signal domain to acquire an analog stimulus signal. The first signal path is operable to forward the analog stimulus signal from the first signal converter to a second signal converter operable to convert the analog stimulus signal back from the analog signal domain to the digital signal domain. The second signal path is operable to forward one of the conversion clock signal and a signal derived thereof from the first signal converter to the second signal converter. A difference between a propagation delay of an analog stimulus signal in response to a clock cycle of the conversion clock signal via the first signal path and a propagation delay of the conversion clock signal of the clock cycle via the second signal path is within a predetermined tolerance range.

Abstract: An automatic tester, comprising a first signal converter, a first signal path, and a second signal path. The first signal converter is operable to convert, using a conversion clock signal, a signal from a digital signal domain to an analog signal domain to acquire an analog stimulus signal. The first signal path is operable to forward the analog stimulus signal from the first signal converter to a second signal converter operable to convert the analog stimulus signal back from the analog signal domain to the digital signal domain. The second signal path is operable to forward one of the conversion clock signal and a signal derived thereof from the first signal converter to the second signal converter. A difference between a propagation delay of an analog stimulus signal in response to a clock cycle of the conversion clock signal via the first signal path and a propagation delay of the conversion clock signal of the clock cycle via the second signal path is within a predetermined tolerance range.

Abstract: A signal distribution structure for distributing a signal to a plurality of devices includes a first signal guiding structure including a first characteristic impedance. The signal distribution structure also includes a node, wherein the first signal guiding structure is coupled to the node. The signal distribution structure includes a second signal guiding structure including one or more transmission lines. The one or more transmission lines of the second signal guiding structure are coupled between the node and a plurality of device connections. The second signal guiding structure includes, side-viewed from the node, a second characteristic impedance which is lower than the first characteristic impedance. The signal guiding structure also includes a matching element connected to the node.

Abstract: A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.

Abstract: A signal distribution structure for distributing a signal to a plurality of devices includes a first signal guiding structure including a first characteristic impedance. The signal distribution structure also includes a node, wherein the first signal guiding structure is coupled to the node. The signal distribution structure includes a second signal guiding structure including one or more transmission lines. The one or more transmission lines of the second signal guiding structure are coupled between the node and a plurality of device connections. The second signal guiding structure includes, side-viewed from the node, a second characteristic impedance which is lower than the first characteristic impedance. The signal guiding structure also includes a matching element connected to the node.

Abstract: A chip tester for testing at least two devices under test connected to the chip tester has a timing calculator for generating a timing information for the channels of the chip tester. The timing calculator is adapted to obtain a propagation delay difference information describing a difference between, on the one hand, a propagation delay from the first channel port of the chip tester to the first terminal of the first device under test and, on the other hand, a propagation delay from the first channel port of the chip tester to the second terminal of the second device under test. The timing calculator is adapted to provide a timing information for a second channel of the chip tester connected to the first device under test or to the second device under test on the basis of the propagation delay difference information. The channel module configurator is adapted to configure the second channel of the chip tester on the basis of the timing information.

Abstract: A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested.

Abstract: A coupling unit is adapted to be coupled between a first and a second unit to be tested. Said coupling unit comprises a first signal path that is adapted to provide a signal connection between at least one terminal of the first unit to be tested and at least one terminal of the second unit to be tested. The first signal path comprises a signal conditioning facility adapted for receiving a first signal from the first unit to be tested, for conditioning said first signal in accordance with predefined parameters, and for providing the conditioned first signal to the second unit to be tested.

Abstract: There is provided a method of source synchronous sampling, where a first clock signal of a first unit is synchronized to a second signal received from a second unit. The method includes determining a timing control signal on the base of the first clock signal and the second signal, generating an adjusted clock signal by adjusting the timing of the first clock signal corresponding to the timing control signal, and using the adjusted clock signal for sampling a signal received from the second unit. The second signal is a clock signal received from the second unit, the adjusted clock signal is used for sampling this clock signal itself, and a corresponding sampled clock signal is supervised to show proper clock functionality.

Abstract: There is provided a method that includes (a) sampling a data signal and a clock signal by applying strobes for obtaining a corresponding bit values each for the data signal and for the clock signal, each of the strobes having a different phase offset with respect to a tester clock signal, (b) deriving first comparison results for the bit values of the data signal by comparing the bit values of the data signal each with an expected data bit value of expected data, (c) deriving second comparison results for the bit values of the clock signal by comparing the bit values of the clock signal each with an expected clock bit value, (d) deriving for the strobes combined comparison results by applying logical operations each on pairs of corresponding first and second comparison results, and (e) deriving a test result based on the combined comparison results.

Abstract: A method of testing a device under test, which is adapted to transmit a digital data signal and a clock signal, the data signal being related to the clock signal, comprising the steps of: sampling within one tester clock cycle of the test device the data signal and the clock signal by applying a number of strobes for obtaining a corresponding number of bit values each for the data signal and for the clock signal, each of the strobes having a different phase offset with respect to a tester clock signal of the test device, deriving first comparison results for the sampled bit values of the data signal by comparing the sampled bit values of the data signal each with an expected data bit value according to expected data, deriving second comparison results for the sampled bit values of the clock signal by comparing the sampled bit values of the clock signal each with an expected clock bit value, deriving for the strobes combined comparison results by applying logical operations each on pairs of corresponding first

Abstract: A method for determining the amount of deterministic jitter and random jitter in a digital signal having transitions between logical levels, the method comprising the steps of: providing said digital signal, determining a plurality of bit error rate values, each bit error rate value being associated with one of a plurality of successive timing points, and each bit error rate value being derived from a comparison of a result of a detection of a transition occurring in the digital signal cumulatively prior to its associated timing point with an expected signal, applying a polynomial fit in time to said plurality of bit error rate values associated with said timing points for determining a number of polynomial coefficients of said polynomial fit, and deriving the amount each of said deterministic and said random jitter from said polynomial coefficients.

Abstract: The invention relates to source synchronous sampling by synchronizing a first clock signal of a first unit to a data signal received from a second unit, comprising the steps of measuring a phase difference between the first clock signal and a second signal, and generating a corresponding timing control signal, generating an adjusted clock signal by adjusting the timing of the first clock signal corresponding to the timing control signal, and generating sampled data by using the adjusted clock signal for sampling the received data signal.

Abstract: A plurality of error values are determined for providing a jitter analysis for a digital signal having transitions between logical levels. Each error value is associated with one of a plurality of successive timing points, and is derived from a comparison of a result of a detection for a transition occurring in the digital signal at its associated timing point with an expected signal. An error signal is provided representing the derived error values relative to their respective timing points, and a spectral jitter analysis is provided for the error signal in order to detect spectral components in the error signal.