Abstract: An improved touch screen controller including a comparator and an analog-to-digital converter. The comparator of the touch screen controller detects a touch of the touch screen while the analog-to-digital converter is powered down. The Data Out (DOUT) line of the touch screen controller is used to signal the microprocessor that a touch has occurred. The unique structure of the improved touch screen controller and the fast switching edges of the comparator output signal provide for a faster touch screen controller that consumes little power without requiring a dedicated pin for the touch signal.

Abstract: A capacitor array is configured to negate or cancel the voltage coefficient of the capacitors within the array, and thus reduce and/or eliminate the voltage coefficient non-linearities present within the A/D converter. In the capacitor array, a first capacitor is suitably configured with at least one additional capacitor in the array such that the charge across the array is linear with respect to an input voltage applied to the input of the array. In addition, the voltage coefficient non-linearities of the first capacitor can be suitably canceled by the inverse voltage coefficient non-linearities of any additional capacitors within the balance of the array, thereby reducing the potential for non-linearities within the A/D converter.

Abstract: A touch screen digitizing system includes a touch screen unit including a first resistive sheet with opposed x+ and x− terminals and a second resistive sheet with opposed y+ and y− terminals, and an ADC having first and second reference input terminals. A first switch is coupled between a first reference voltage and the x− terminal, and a second switch is coupled between the x+ terminal and a second reference voltage for energizing the first resistive sheet. A third switch is coupled between the first reference voltage and the y− terminal, and a fourth switch is coupled between the y+ terminal and the second reference voltage for energizing the second resistive sheet.

Abstract: Power control circuitry is provided in an analog-to-digital converter (1) having a CDAC array (2) coupled to an analog input signal, a comparator (3), and a successive approximation register circuit (5). The power control circuitry includes a bias control circuit (4) responsive to a powerdown signal and associated wakeup signal to produce a bias control signal (V.sub.BIAS). The bias control circuit includes a controllable current mirror circuit (10) which produces a first voltage (V.sub.C) on a first conductor (13) when the powerdown signal is at a first level to allow operation of the comparator in conjunction with the CDAC array and the successive approximation register circuit. The bias control circuit also includes a wakeup circuit (20) which precharges the first conductor (13) to a predetermined bias voltage (V.sub.C ') that is close in value to the first voltage (V.sub.C) in response to occurrence of the first level of the powerdown signal. The bias control signal V.sub.

Abstract: A conversion circuit digitizes first and second differential analog signals conducted by first and second conductors for digital processing in a motor control system. The conversion circuit includes an analog-to-digital conversion circuit. The analog-to-digital conversion circuit includes a CDAC having a charge summing conductor connected to an input of a bit decision comparator and first and second simultaneously sampled differential sample and hold MSB circuits connected to the charge summing conductor. The first and second differential analog signals are simultaneously sampled and held in the first and second differential sample and hold MSB circuits, respectively, and then are sequentially converted to digital numbers by the analog-to-digital conversion circuit.

Abstract: A reference voltage circuit in an integrated circuit analog-to-digital converter includes a band gap circuit, a first field effect transistor coupling an output conductor of the band gap circuit to a first external bypass capacitor and a non-inverting input of a buffer circuit. A second field effect transistor couples the first conductor to a non-inverting input of the buffer circuit. An output of the buffer circuit is coupled to an inverting input thereof. The first and second field effect transistors are turned on during conversions, during which the first field effect transistor and the first bypass capacitor coacting to filter high frequency noise produced by the band gap circuit to apply a precise reference voltage to the non-inverting input of the buffer circuit.

Abstract: A circuit for preventing analog-to-digital conversion errors due to MOS threshold shifts produced in a comparator during successive approximation testing of MSB and LSB groups of binarily weighted bit capacitors includes a first amplifier that amplifies voltage changes produced on a charge distribution conductor connected to the bit capacitors during successive approximation testing of the bit capacitors of the MSB group. The output of the first amplifier subjects a MOSFET in an input stage of the comparator to sufficiently large gate-to-source voltages to produce an MOS threshold shift in the MOSFET. During successive approximation testing of bit capacitors of the LSB group, a second amplifier amplifies signals representative of voltage changes produced on the charge distribution conductor and applies the amplified signals to the same MOSFET.